GLT6400L08LL-85ST 데이터 시트보기 (PDF) - G-Link Technology
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GLT6400L08LL-85ST Datasheet PDF : 10 Pages
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G-LINK
GLT6400L08
Ultra Low Power 512k x 8 CMOS SRAM
Feb 2001(Rev. 1.1)
Timing Waveform of Read Cycle 1 (3,6,7,9) (Address Controlled)
Address
tRC
tAA
tOH
DOUT
Data Valid
Timing Waveform of Read Cycle 2 (5,6,8,9) ( CE1 Controlled)
CE1
tRC
OE
tOE
tACE
tOLZ
tOHZ
tCHZ
DOUT
tCLZ
Data Valid
Supply Current
tPU
50%
tPD
ICC
50%
ISB
Write Cycle (3,11)( 70ns Vcc=3V to 3.6V , 85ns Vcc=2.7V to 3.3V )
Parameter
Write Cycle Time
Chip Enable to Write End
Address Setup to Write End
Address Setup Time
Write Pulse Width
Write Recovering Time
Data Valid to Write End
Data Hold Time
Write Enable to Output in High-Z
Output Active from Write End
G-Link Technology Corporation
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
70
Symbol
Min Max
85
Unit Note
Min Max
tWC
70
85
ns
tCW
60
70
ns
tAW
60
70
ns
tAS
0
0
ns
tWP
50
60
ns
tWR
0
0
ns
tDW
30
35
ns
tDH
0
0
ns
tWZ
25
35 ns 4,5
tOW
5
5
ns 4,5
-6-
G-Link Technology Corporation, Taiwan
6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
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