MP7641AN 데이터 시트보기 (PDF) - Exar Corporation

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MP7641AN

8-Channel Voltage Output 10 MHz Input Bandwidth 8-Bit Multiplying DACs with Serial Digital Port

Exar Corporation 

MP7641

THEORY OF OPERATION

The MP7641 is equipped with a serial data 3-wire standard

µ-processor logic interface to reduce pin count, package size,

and board wire (space). This interface consists of LD which con-

trols the transfer of data to the selected DAC channel, SDI (serial

data/address input), CLK (shift register clock) and SDO (serial

data output). When the LD signal is high, CLK signal loads the

digital input bits (SDI) into the 12-bit shift register (4 bits address

A3 to A0, then 8 bits data D7 to D0). The LD signal going low

loads this data into the selected DAC. The LD signal going low

also disables the serial data input (SDI), output (SDO 3-stated)

and the CLK input. This design tremendously reduces digital

noise, and glitch transients into the DACs due to free running

CLK and SDI. Also, 3-stating the SDO output with LD signal

would allow read back of pre-stored digital data of the selected

package using one SDO wire for all DAC ICs on the board. Note

also that the reset signal (RST) resets all analog outputs to 1/2 of

VREF, regardless of any digital inputs. Note that the input VRi is

referenced to AGND.

Function A3 A2 A1 A0

LD

CLK RST

SDI

Shift Data In

and Out

X XX X

1

0→1

Repeat

1

Stop Shifting X X X X

0

Data In and

Out

X

1

Load DACs

DAC 0

DAC 1

DAC 2

DAC 3

DAC 4

DAC 5

DAC 6

DAC 7

0 00 0

0 00 1

No 1O→pe0ration

X

1

0 01 0

1→0

X

1

0 01 1

1→0

X

1

0 10 0

1→0

X

1

0 10 1

1→0

X

1

0 11 0

1→0

X

1

0 11 1

1→0

X

1

1 00 0

1→0

X

1

No Operation

X

X

X

1 1 1 0 No Operation

X

1

1 1 1 1 No Operation

X

1

Data Input

Valid

X

X

X

X

X

X

X

X

X

X

X

Reset all DACs to X X X X

X

VREF/2

X

0

X

SDO

Data Output

Valid

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

X

Table 1. Digital Function Truth Table

Serial In/Serial Out

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DAC Output Voltage

MSB

LSB

VOi

= AGND + (VRi –

AGND)

(

D

256

)

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

AGND

(VRi

– AGND)

(

1

256

)

+ AGND

1

1

1

1

1

1

1

0

1

1

1

1

1

1

1

1

(VRi

– AGND)

(

254

256

)

+

AGND

(VRi

– AGND)

(

255

256

)

+

AGND

Rev. 2.00

Table 2. DAC Transfer Function

Analog Output vs. Digital Code

9

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