MP7641AN 데이터 시트보기 (PDF) - Exar Corporation
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MP7641AN
Exar Corporation
MP7641AN Datasheet PDF : 24 Pages
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MP7641
ELECTRICAL CHARACTERISTICS TABLE
Description
25°C
Tmin to Tmax
Symbol Min Typ Max Min Max Units
DIGITAL TIMING
SPECIFICATIONS2, 4
Input Clock Pulse Width
tCH, tCL
40
Data Setup Time
tDS
10
Data Hold Time
tDH
15
CLK to SDO Propagation Delay
tPD
DAC Register Load Pulse Width
tLD
100
Reset Pulse Width
tRST
50
Clock Edge to Load Rising Edge
tCKLD1
100
Clock Edge to Load Falling Edge tCKLD2
0
Load Falling Edge to SDO
tHZ1
50
3-state Enable
Load Rising Edge to SDO
3-state Disable
tHZ2
35
Load Falling Edge to CLK Disable tLDCK1
25
Load Rising Edge to CLK Enable tLDCK2
35
LD Set-up Time with Respect
tLDSU
15
to CLK
50
ns
10
ns
15
ns
40
50 ns
100
ns
60
ns
100
ns
0
ns
60
ns
50
ns
40
ns
50
ns
20
ns
Conditions
NOTES
1 Full Scale Range (FSR) is 3V.
2 Guaranteed but not production tested.
3 Digital input levels should not go below ground or exceed the positive supply voltage, otherwise damage may occur.
4 See Figures 2 and 3.
5 For reference input pulse: tR = tF > 100 ns.
Specifications are subject to change without notice
Rev. 2.00
5
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