PCK2510SLDH 데이터 시트보기 (PDF) - Philips Electronics

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PCK2510SLDH

50–150 MHz 1:10 SDRAM clock driver

Philips Electronics 

Philips Semiconductors

50–150 MHz 1:10 SDRAM clock driver

Product specification

PCK2510SL

TIMING REQUIREMENTS

Over recommended ranges of supply voltage and operating free-air temperature

SYMBOL

PARAMETER

MIN

MAX

UNIT

fCLK Clock frequency

Input clock duty cycle

50

150

MHz

40

60

%

Stabilization time1

1

ms

NOTE:

1. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained,

a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation

delay, skew, and jitter parameters given in the switching characteristics table are not applicable.

SWITCHING CHARACTERISTICS

Over recommended ranges of supply voltage and operating free-air temperature; CL = 30 pF

PARAMETER

FROM

(INPUT)/CONDITION

TO

(OUTPUT)

tphase error 2

CLKIN↑ = 100 MHz to 133 MHz

CLKIN↑ = 66 MHz

FBIN↑

FBIN↑

tphase error – jitter 1, 3 CLKIN↑ = 100 MHz to 133 MHz

FBIN↑

tSK(0)

Any Y or FBOUT

Any Y or FBOUT

jitter(peak-peak)

jitter (cycle-cycle) 1

Duty cycle reference 1

CLKIN = 100 MHz to 133 MHz

F(CLKIN > 60 MHz)

Any Y or FBOUT

Any Y or FBOUT

tr 1

VO = 0.4 V to 2 V

Any Y or FBOUT

tf 1

VO = 0.4 V to 2 V

Any Y or FBOUT

NOTES:

1. These parameters are not production tested.

2. This is considered as static phase offset.

3. Phase error does not include jitter. (tphase error = static phase error – jitter(cycle-cycle))

4. The tSK(0) specification is only valid for outputs with equal loading.

VCC, AVCC = 3.3 V ±0.3 V

MIN

TYP

MAX

–100

100

–125

125

–50

50

200

–80

80

|65|

47

53

2.5

1

2.5

1

UNIT

ps

ps

ps

ps

ps

%

V/ns

V/ns

2000 Dec 01

6

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