PCF8577CT/3,118 데이터 시트보기 (PDF) - NXP Semiconductors.
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PCF8577CT/3,118 Datasheet PDF : 33 Pages
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NXP Semiconductors
PCF8577C
LCD direct/duplex driver with I²C-bus interface
Table 5. Segment byte-segment driver mapping in direct drive mode
Mode Bank V2 V1 V0 Segment/ 7
6
5
4
3
2
1
0
Backplane
Bit/
MSB
LSB
Register
0
0
0000
S8 S7 S6 S5 S4 S3 S2 S1 BP1
0
1
0011
S8 S7 S6 S5 S4 S3 S2 S1 BP1
0
0
0102
S16 S15 S14 S13 S12 S11 S10 S9 BP1
0
1
0113
S16 S15 S14 S13 S12 S11 S10 S9 BP1
0
0
1004
S24 S23 S22 S21 S20 S19 S18 S17 BP1
0
1
1015
S24 S23 S22 S21 S20 S19 S18 S17 BP1
0
0
1106
S32 S31 S30 S29 S28 S27 S26 S25 BP1
0
1
1117
S32 S31 S30 S29 S28 S27 S26 S25 BP1
Mapping example: bit 0 of register 7 controls the LCD segment S25 if BANK bit is a
logic 1.
Table 6. Segment byte-segment driver mapping in duplex mode
Mode Bank V2 V1 V0 Segment/ 7
6
5
4
3
2
1
0
Backplane
Bit/
MSB
LSB
Register
1
X[1] 0 0 0 0
S8 S7 S6 S5 S4 S3 S2 S1 BP1
1
X[1] 0 0 1 1
S8 S7 S6 S5 S4 S3 S2 S1 BP2
1
X[1] 0 1 0 2
S16 S15 S14 S13 S12 S11 S10 S9 BP1
1
X[1] 0 1 1 3
S16 S15 S14 S13 S12 S11 S10 S9 BP2
1
X[1] 1 0 0 4
S24 S23 S22 S21 S20 S19 S18 S17 BP1
1
X[1] 1 0 1 5
S24 S23 S22 S21 S20 S19 S18 S17 BP2
1
X[1] 1 1 0 6
S32 S31 S30 S29 S28 S27 S26 S25 BP1
1
X[1] 1 1 1 7
S32 S31 S30 S29 S28 S27 S26 S25 BP2
[1] Don’t care.
Mapping example: bit 7 of register 5 controls the LCD segment S24/BP2.
7.8 Power-on reset
At power-on reset the PCF8577C resets to a defined starting condition as follows:
1. Both backplane outputs are set to VSS in master mode; to 3-state in cascade mode
2. All segment outputs are set to VSS
3. The segment byte registers and control register are cleared
4. The I2C-bus interface is initialized.
PCF8577C
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 10 October 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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