PCF8577CT/3,118 데이터 시트보기 (PDF) - NXP Semiconductors.

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PCF8577CT/3,118

LCD direct/duplex driver with I²C-bus interface

NXP Semiconductors. 

NXP Semiconductors

PCF8577C

LCD direct/duplex driver with I²C-bus interface

7.3 User-accessible registers

There are nine user-accessible 1-byte registers. The first is a control register which is

used to control the loading of data into the segment byte registers and to select display

options. The other eight are segment byte registers, split into two banks of storage, which

store the segment data. The set of even-numbered segment byte registers is called

BANK A. Odd-numbered segment byte registers are called BANK B.

There is one slave address for the PCF8577C (see Table 7). All addressed devices load

the second byte into the control register and each device maintains an identical copy of

the control byte in the control register always (see I2C-bus protocol, Figure 10), i.e. all

addressed devices respond to control commands sent on the I2C-bus.

The control register is shown in more detail in Figure 3. The least-significant bits select

which device and which segment byte register is loaded next. This part of the register is

therefore called the Segment Byte Vector (SBV).

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Fig 3. PCF8577C register organization

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The upper three bits of the SBV (V5 to V3) are compared with the hardware subaddress

input signals A2, A1 and A0. If they are the same, then the device is enabled for loading, if

not the device ignores incoming data but remains active.

The three least-significant bits of the SBV (V2 to V0) address one of the segment byte

registers within the enabled chip for loading segment data.

PCF8577C

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 5 — 10 October 2014

© NXP Semiconductors N.V. 2014. All rights reserved.

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