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PCA9542A Datasheet PDF : 22 Pages
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NXP Semiconductors
PCA9542A
2-channel I2C-bus multiplexer and interrupt logic
Table 4. Control register: Write—channel selection; Read—channel status
D7 D6 INT1 INT0 D3 B2 B1 B0 Command
X
X
X
X
X
0
X
X
no channel selected
X
X
X
X
X
1
0
0
channel 0 enabled
X
X
X
X
X
1
0
1
channel 1 enabled
X
X
X
X
X
1
1
X
no channel selected
0
0
0
0
0
0
0
0
no channel selected;
power-up default state
6.3 Interrupt handling
The PCA9542A provides 2 interrupt inputs, one for each channel and one open-drain
interrupt output. When an interrupt is generated by any device, it will be detected by the
PCA9542A and the interrupt output will be driven LOW. The channel need not be active
for detection of the interrupt. A bit is also set in the control byte.
Bits 5:4 of the control byte correspond to channel 1, channel 0 of the PCA9542A,
respectively. Therefore, if an interrupt is generated by any device connected to channel 1,
the state of the interrupt inputs is loaded into the control register when a read is
accomplished. Likewise, an interrupt on any device connected to channel 0 would cause
bit 4 of the control register to be set on the read. The master can then address the
PCA9542A and read the contents of the control byte to determine which channel contains
the device generating the interrupt. The master can then reconfigure the PCA9542A to
select this channel, and locate the device generating the interrupt and clear it.
It should be noted that more than one device can be providing an interrupt on a channel,
so it is up to the master to ensure that all devices on a channel are interrogated for an
interrupt.
The interrupt inputs may be used as general purpose inputs if the interrupt function is not
required.
If unused, interrupt input(s) must be connected to VDD through a pull-up resistor.
Table 5. Control register read — interrupt
D7 D6 INT1 INT0 D3 B2 B1 B0 Command
0
no interrupt on channel 0
0
0
X
X
X
X
X
1
interrupt on channel 0
0
no interrupt on channel 1
0
0
X
X
X
X
X
1
interrupt on channel 1
Remark: The two interrupts can be active at the same time.
6.4 Power-on reset
When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9542A in
a reset condition until VDD has reached VPOR. At this point, the reset condition is released
and the PCA9542A registers and I2C-bus state machine are initialized to their default
states (all zeroes), causing all the channels to be deselected. Thereafter, VDD must be
lowered below 0.2 V to reset the device.
PCA9542A_3
Product data sheet
Rev. 03 — 24 November 2008
© NXP B.V. 2008. All rights reserved.
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