NJU3754
SWITCHING CHARACTERISTICS
PARAMETER
CLK Cycle Time
SYMBOL
tCYC
(VDD=2.7~5.5V, VSS=0V, Ta=25°C, unless otherwise noted)
CONDITION
MIN
TYP
MAX UNIT
CLK
200
-
-
ns
CLK Pulse Width (H)
tWCH
CLK
90
-
-
ns
CLK Pulse Width (L)
CE Pulse Width (H)
tWCL
tWEH
CLK
CE
90
-
100
-
-
ns
-
ns
CE Set-up Time before CLK Falling
tSS
CE - CLK
100
-
CE Hold Time after CLK Falling
tHS
CLK - CE
100
-
Parallel Data Set-up Time
tSPL
P0~P10 - CE
50
-
Parallel Data Hold Time
tHPL
CE - P0~P10
50
-
SO Delay Time after CE Falling
tDSL
CE - SO (Note 6)
-
-
SO Delay Time after CLK Falling
tDSS
CLK - SO (Note 6)
-
-
SO Hold Time after CE Rising
tDSZ
CE - SO (Note 6)
-
-
Rise Time
tR
CLK Terminal
-
-
ns
ns
-
ns
-
ns
50
ns
50
ns
20
ns
20
ns
Fall Time
tF
CLK, CE Terminals
-
Note 5) A 15kΩ pull-up or pull-down resistor and a 50pF capacitor on the SO terminal.
Note 6) All timings are based on 30% and 70% voltage level of VDD.
-
20
ns
-4-
Ver.2004-03-15