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NJU3754

11-BIT PARALLEL TO SERIAL CONVERTER

Japan Radio Corporation  

NJU3754

TERMINAL DESCRIPTION

No.

SYMBOL

I/O

1

P0

I

2

P1

I

3

P2

I

4

P3

I

5

P4

I

6

P5

I

7

P6

I

8

VSS

-

9

P7

I

10

P8

I

11

P9

I

12

P10

I

13

SO

O

14

CLK

I

15

CE

I

16

VDD

-

FUNCTION

Parallel Data Input Terminals (with pull-up resistors)

Ground

Parallel Data Input Terminals (with pull-up resistors)

Serial Data Output Terminal

Serial Clock Input Terminal

Chip Enable Input Terminal

Power Supply Terminal (2.7 to 5.5V)

FUNCTIONAL DESCRIPTION

At the falling edge of CE terminal, the status of P0 to P10 terminal is latched and transferred to the shift

register. At the mean time, the P0 data is output from SO terminal. While CE terminal is “L”, the data from

P1 to P10 in the shift register are synchronized with the falling edge of CLK terminal and output from SO

terminal.

When CE terminal is “H”, SO terminal is high impedance.

Note 1) If the 11th falling edge and later are input to CLK terminal while CE is “L”, the 12th and the following data are invalid.

CE

CLK

SO

P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 Invalid

P0~P10

Valid

-2-

Ver.2004-03-15

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