NJU3503L 데이터 시트보기 (PDF) - Japan Radio Corporation

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NJU3503L

4-BIT SINGLE CHIP MICRO CONTROLLER

Japan Radio Corporation  

NJU3503

In case of the external clock operation, the external clock is input as the SCK clock to the SCK terminal as

shown in the serial transmission timing chart. The signal condition into the SCK terminal must be kept as

“HIGH” until the external clock come in. In the transmission, when the SCK with the noise or other redundant

signals from the outside of the NJU3503 input to the SCK terminal, Serial Input Output operates incorrectly.

The maximum frequency of the SCK is 500kHz.

In case of the internal clock operation, the SCK outputs through the SCK terminal as shown in the serial

transmission timing chart. The internal interrupt signal occurs when the 3-bit counter has counted the SCK

clock up to 8 times that means 1-byte serial data transmission end. The internal clock as the SCK is the

divided clock in the internal prescaler, and the frequency of the clock can be selected by the mask option from

follows which are dividing numbers based on the inverse of the 1-instruction executing period(1/fOSC x 6).

1/2, 1/4, 1/8, 1/16, 1/32,1/64, 1/128, 1/256, 1/512, 1/1024, 1/2048,1/4096

Remarks 1) When the bit2(b2) of Timer1 / Prescaler control register(PHY3) is set to "1", the prescaler generating

the internal serial clock is stopped and the internal serial clock is also stopped. Accordingly, Serial Input

Output does not operate.

Remarks 2) If the writing operation is operated to the Serial Input / Output shift register(PHY2) or the Serial Input /

Output control register during the transmission or the reception operation, the 3-bit counter is reset and

the serial data transmission or reception is stopped. Therefore the writing operation to the above

registers must not be operated during the transmission or reception operation.

• SERIAL INPUT / OUTPUT CONTROL REGISTER { PHY1 ; (Y'=1) }

When the data of bit1(b1) and bit3(b3) of the Serial Input / Output control register are changed, the

operation must be performed before starting the serial transmission. (See the following sample program)

In changing the condition of b1 or b2 of PHY1 and setting the LSB of PHY1 to start the transmission are

operated in the mean time, Serial Input Output operation does not operate correctly.

[ Writing to the Serial Input / Output Control Register ]

(MSB) 3

2

1

0 (LSB)

PHY1

−

Serial Input Output control

Shift Clock mode

SDI(O) terminal mode

/ 1:Start

/ 0:Internal Clock,

1:External Clock

/ 0:Input, 1:Output

EX.) An example of the start procedure in the 3-wire serial data transmission, the external clock operation

and the SDI(O) terminal setting as the input.

:

:

SRPC

LDI Y,1

LDI A,%0010

TAP

LDI A,%0011

TAP

:

:

;

;PHY1(Serial Input / Output control register) is pointed

;"0010"(BIN) is stored to accumulator

External clock,

;Data is transferred from accumulator to PHY1 Input mode

;"0011"(BIN) is stored to accumulator

Transmission

;Data is transferred from accumulator to PHY1 Starts.

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