NJU3503L 데이터 시트보기 (PDF) - Japan Radio Corporation

부품명

상세내역

일치하는 목록

NJU3503L

4-BIT SINGLE CHIP MICRO CONTROLLER

Japan Radio Corporation  

NJU3503

An example of the serial data reception program)

In the internal clock operation, SDI(O) terminal is set as the input and the serial input data is transferred

to RAM.

:

:

;---- Interrupt process ----

ORG $40

;Interrupt vector address of FULL or EMPTY

SINT

SRPC

;

LDI Y,1

;The Serial Input / Output control register is set

TPA

;

TBA 0

;The end flag of transmission is tested

JMP SIO_OK

;

JMP SINT_E

;

;

SIO_OK LDI Y,2

;The Serial Input / Output shift register is set

RRPC

;RAM to store the serial input data is pointed

LDI X,SIO_DAT.X

;RAM address, X=0

LDI Y,SIO_DAT.Y

;RAM address, Y=0

TPMICY

;The serial input data is transferred to RAM(lower 4-bit)

; and Y-register is incremented

TPMICY

;The serial input data is transferred to RAM(higher 4-bit)

; and Y-register is incremented

;

SINT_E RETI

; End of the interrupt process

;

;------ Serial data inputting process ------

SIO_IN SRPC

;

LDI Y,0

;The peripheral register table is set

CLA

;

TAP

;

LDI Y,1

;The Serial Input / Output control register is set

LDI A,%0000

;The internal clock operation is set and the SDI(O)

; terminal is set as the input

TAP

;

LDI A,%0001

;The serial data reception is started

TAP

;

;

:

:

WSEG

;The RAM area is set

SIO_DAT DS

2

;The area to store the serial input data is secured

- 31 -

Share Link: