MT90823AB1 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc

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MT90823AB1

3 V Large Digital Switch

Zarlink Semiconductor Inc 

MT90823

Data Sheet

Pin Description (continued)

Pin #

84 100 100

PLCC MQFP LQFP

50

23

20

120

BGA

M10

51

24

21

N12

52

25

22

M11

53

26

23

N13

55 - 32-39 29 -

62

36

L12,L13,K12,

K13,J12,J13,

H12,H13

65 - 42-49 39 -

72

46

73

50

47

G12,G13,F12,

F13,E12,E13,

D12,D13

C12

74

55

48

C13

Name

Description

R/W / WR Read/Write / Write (5 V Tolerant Input): In the cases

of Motorola non-multiplexed and multiplexed bus

operations, this input is R/W. This input controls the

direction of the data bus lines (AD0 - AD7, D8-D15)

during a microprocessor access.

For multiplexed bus operation, this input is WR. This

active low input is used with RD to control the data bus

(AD0 - 7) lines as inputs.

CS Chip Select (5 V Tolerant Input): Active low input

used by a microprocessor to activate the

microprocessor port of MT90823.

AS/ALE

Address Strobe or Latch Enable (5 V Tolerant

Input): This input is used if multiplexed bus operation

is selected via the IM input pin. For Motorola non-

multiplexed bus operation, connect this pin to ground.

IM CPU Interface Mode (5 V Tolerant Input): When IM is

high, the microprocessor port is in the multiplexed

mode. When IM is low, the microprocessor port is in

non-multiplexed mode.

AD0 - 7

Address/Data Bus 0 to 7 (5 V Tolerant I/O): These

pins are the eight least significant data bits of the

microprocessor port. In multiplexed mode, these pins

are also the input address bits of the microprocessor

port.

D8 - 15 Data Bus 8-15 (5 V Tolerant I/O): These pins are the

eight most significant data bits of the microprocessor

port.

DTA Data Transfer Acknowledgement (5 V tolerant

Three-state Output): Indicates that a data bus transfer

is complete. When the bus cycle ends, this pin drives

HIGH and then tri-states, allowing for faster bus cycles

with a weaker pull-up resistor. A pull-up resistor is

required to hold a HIGH level when the pin is tri-stated.

CSTo

Control Output (5 V Tolerant Output). This is a

4.096, 8.192 or 16.384 Mb/s output containing 512,

1024 or 2048 bits per frame respectively. The level of

each bit is determined by the CSTo bit in the

connection memory. See External Drive Control

Section.

7

Zarlink Semiconductor Inc.

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