MT90823AB1 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc

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MT90823AB1

3 V Large Digital Switch

Zarlink Semiconductor Inc 

MT90823

Data Sheet

Pin Description

Pin #

84 100 100

PLCC MQFP LQFP

120

BGA

Name

Description

1, 11, 31, 41, 28, A1,A2,A12,A13,

30, 54 56, 66, 38, B1,B2,B7,B12,

VSS Ground.

64, 75 76, 99 53, B13,C3,C5,C7,

63, C9,C11,E3,E11

73, G3,G11,J3,J11,

96 L3,L5,L7,L9,L11,

M1,M2,M12,M13

2, 32,

63

5, 40,

67

37,

64,98

C4,C6,C8,C10,

D3,D11,F3,F11,

H3,H11,K3,K11,

L4,L6,L8,L10

VDD +3.3 Volt Power Supply.

3 - 10 68-75 65 - B6,A6,A5,B5,A4, STo8 - 15 ST-BUS Output 8 to 15 (5 V Tolerant Three-state

72

B4,A3,B3

Outputs): Serial data Output stream. These streams

may have data rates of 2.048, 4.096 or 8.192 Mb/s,

depending upon the value programmed at bits DR0 - 1

in the IMS register.

12 - 81-96 78 - C1,C2,D1,D2,E1, STi0 - 15 ST-BUS Input 0 to 15 (5 V Tolerant Inputs): Serial

27

93 E2,F1,F2,G1,G2,

data input stream. These streams may have data rates

H1,H2,J1,J2,K1,

of 2.048, 4.096 or 8.192 Mb/s, depending upon the

K2

value programmed at bits DR0 - 1 in the IMS register.

28

97

94

L1

F0i Frame Pulse (5 V Tolerant Input): When the WFPS

pin is low, this input accepts and automatically

identifies frame synchronization signals formatted

according to ST-BUS and GCI specifications. When the

WFPS pin is high, this pin accepts a negative frame

pulse which conforms to WFPS formats.

29

98

95

L2

FE/HCLK Frame Evaluation / HCLK Clock (5 V Tolerant

Input): When the WFPS pin is low, this pin is the frame

measurement input. When the WFPS pin is high, the

HCLK (4.096MHz clock) is required for frame

alignment in the wide frame pulse (WFP) mode.

31 100 97

N1

CLK Clock (5 V Tolerant Input): Serial clock for shifting

data in/out on the serial streams (STi/o 0 - 15).

Depending upon the value programmed at bits DR0 - 1

in the IMS register, this input accepts a 4.096, 8.192 or

16.384 MHz clock.

33

6

3

N2

TMS Test Mode Select (3.3 V Input with internal pull-up):

JTAG signal that controls the TAP controller state

transitions.

34

7

4

M3

TDI Test Serial Data In (3.3 V Tolerant Input with internal

pull-up): JTAG serial test instructions and data are

shifted in on this pin.

5

Zarlink Semiconductor Inc.

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