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MT9043

T1/E1 System Synchronizer

Zarlink Semiconductor Inc 

MT9043

Data Sheet

As shown in Table 3, the Mode/Control Select pin MS selects the mode. Refer to Table 4 and Figure 7 for details of

the state change sequences.

Normal Mode

Normal Mode is typically used when a slave clock source, synchronized to the network is required.

In Normal Mode, the MT9043 provides timing (C1.5o, C2o, C4o, C8o, C16o and C19o) and frame synchronization

(F0o, F8o, F16o, TSP and RSP) signals, which are synchronized to one of two reference inputs (PRI or SEC). The

input reference signal may have a nominal frequency of 8kHz, 1.544MHz, 2.048MHz or 19.44MHz.

From a reset condition, the MT9043 will take up to 30 seconds (see AC Electrical Characteristics) of input reference

signal to output signals which are synchronized (phase locked) to the reference input.

The selection of input references is control dependent as shown in state table 4. The reference frequencies are

selected by the frequency control pins FS2 and FS1 as shown in Table 1.

Fast Lock Mode

Fast Lock Mode is a submode of Normal Mode, it is used to allow the MT9043 to lock to a reference more quickly

than Normal mode will allow. Typically, the PLL will lock to the incoming reference within 500 ms if the FLOCK pin is

set high.

Freerun Mode

Freerun Mode is typically used when a master clock source is required, or immediately following system power-up

before network synchronization is achieved.

In Freerun Mode, the MT9043 provides timing and synchronization signals which are based on the master clock

frequency (OSCi) only, and are not synchronized to the reference signals (PRI and SEC).

The accuracy of the output clock is equal to the accuracy of the master clock (OSCi). So if a ±32ppm output clock

is required, the master clock must also be ±32ppm. See Applications - Crystal and Clock Oscillator sections.

MT9043 Measures of Performance

The following are some synchronizer performance indicators and their corresponding definitions.

Intrinsic Jitter

Intrinsic jitter is the jitter produced by the synchronizing circuit and is measured at its output. It is measured by

applying a reference signal with no jitter to the input of the device, and measuring its output jitter. Intrinsic jitter may

also be measured when the device is free running by measuring the output jitter of the device. Intrinsic jitter is

usually measured with various bandlimiting filters depending on the applicable standards. In the MT9043, the

intrinsic Jitter is limited to less than 0.02UI on the 2.048MHz and 1.544MHz clocks.

Jitter Tolerance

Jitter tolerance is a measure of the ability of a PLL to operate properly (i.e., remain in lock and or regain lock in the

presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its reference. The applied

jitter magnitude and jitter frequency depends on the applicable standards.

Jitter Transfer

Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter

at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured

with various filters depending on the applicable standards.

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Zarlink Semiconductor Inc.

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