MT9043 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc

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MT9043

T1/E1 System Synchronizer

Zarlink Semiconductor Inc 

MT9043

Data Sheet

VSS

RST

TCLR

IC

SEC

PRI

Vdd

OSCo

OSCi

Vss

F16o

F0o

RSP

TSP

F8o

C1.5o

Vdd

LOCK

C2o

C4o

C19o

FLOCK

Vss

IC

1

48

2

47

3

46

4

45

5

44

6

43

7

42

8

41

9

40

10 MT9043AN 39

11

38

12

37

13

36

14

35

15

34

16

33

17

32

18

31

19

30

20

29

21

28

22

27

23

26

24

25

TMS

TCK

TRST

TDI

TDO

IC

IC

FS1

FS2

IC

RSEL

IC

MS

Vdd

IC

IC

NC

Vss

IC

IM

Vdd

C6o

C16o

C8o

Figure 2 - Pin Connections

Pin Description

Pin #

1,10,

23,31

2

3

4

5

6

7,17

28,35

8

Name

VSS

Ground. 0 Volts. (Vss pads).

Description

RST

TCLR

IC

SEC

PRI

VDD

Reset (Input). A logic low at this input resets the MT9043. To ensure proper operation, the

device must be reset after reference signal frequency changes and power-up. The RST

pin should be held low for a minimum of 300ns. While the RST pin is low, all frame pulses

except RST and TSP and all clock outputs except C6o, C16o and C19o are at logic high.

The RST, TSP, C6o and C16o are at logic low during reset. The C19o is free-running

during reset. Following a reset, the input reference source and output clocks and frame

pulses are phase aligned as shown in Figure 12.

TIE Circuit Reset (Input). A logic low at this input resets the Time Interval Error (TIE)

correction circuit resulting in a realignment of input phase with output phase as shown in

Figure 13. The TCLR pin should be held low for a minimum of 300ns. This pin is internally

pulled down to VSS.

Internal Connection. Leave open circuit.

Secondary Reference (Input). This is one of two (PRI & SEC) input reference sources

(falling edge) used for synchronization. One of four possible frequencies (8kHz, 1.544MHz,

2.048MHz or 19.44MHz) may be used. The selection of the input reference is based upon the

MS, and RSEL, control inputs.This pin is internally pulled up to VDD.

Primary Reference (Input). See pin description for SEC. This pin is internally pulled up to

VDD.

Positive Supply Voltage. +3.3VDC nominal.

OSCo Oscillator Master Clock (CMOS Output). For crystal operation, a 20MHz crystal is

connected from this pin to OSCi, see Figure 9. Not suitable for driving other devices. For

clock oscillator operation, this pin is left unconnected, see Figure 8.

2

Zarlink Semiconductor Inc.

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