MT8985AE1 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc

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MT8985AE1

CMOS ST-BUS™ FAMILY Enhanced Digital Switch

Zarlink Semiconductor Inc 

MT8985

Data Sheet

7

6

5

4

3

2

1

0

X

V/C

X

X

X

MC CSTo OE

BIT

NAME

6

V/C

2

MC

1

CSTo

0

OE

x = Don’t care

DESCRIPTION

Variable/Constant Throughput Delay Mode. This bit is used to select between Variable (LOW)

and Constant Delay (HIGH) modes on a per-channel basis.

Message Channel. When 1, the contents of the corresponding location in Connection Memory

Low are output on the corresponding channel and stream. When 0, the contents of the programmed

location in Connection Memory Low act as an address for the Data Memory and so determine the

source of the connection to the location’s channel and stream.

CSTo Bit. This bit drives a bit time on the CSTo output pin.

Output Enable. This bit enables the output drivers on a per-channel basis. This allows individual

channels on individual streams to be made high-impedance, allowing switch matrices to be

constructed. A HIGH enables the driver and a LOW disables it.

Figure 5 - Connection Memory High Bits

7

6

5

4

3

2

1

0

SAB2 SAB1 SAB0 CAB4 CAB3 CAB2 CAB1 CAB0

BIT

NAME

DESCRIPTION

7-5

SAB2-0* Source Stream Address bits. These three bits are used to select eight source streams for the

connection. Bit 7 of each word is the most significant bit.

4-0* CAB4-0* Source Channel Address bits 0-4. These five bits are used to select 32 different source channels

for the connection (The ST-BUS stream where the channel is present is defined by bits SAB2-0).

Bit 4 is the most significant bit.

*

If bit 2 of the corresponding Connection High location is 1 or if bit 6 of the Control Register is 1, then these entire 8 bits are output on the

channel and stream associated with this location. Otherwise, the bits are used as indicated to define the source of the connection which is

output on the channel and stream associated with this location.

Figure 6 - Connection Memory Low Bits

During the microprocessor initialization routine, the microprocessor should program the desired active paths

through the matrices, and put all other channels into the high impedance state. Care should be taken that no two

connected ST-BUS outputs drive the bus simultaneously. When this process is complete, the microprocessor

controlling the matrices can bring the ODE signal high to relinquish high impedance state control to the CMHb0s.

9

Zarlink Semiconductor Inc.

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