MT8985AE1 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc

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MT8985AE1

CMOS ST-BUS™ FAMILY Enhanced Digital Switch

Zarlink Semiconductor Inc 

MT8985

Data Sheet

7

6

5

4

3

2

1

0

SM ME

X MS1 MS0 STA2 STA1 STA0

BIT

NAME

DESCRIPTION

7

SM

Split Memory. When 1, all subsequent reads are from the Data Memory and writes are to the

Connection Memory Low, except when the Control Register is accessed again. The Memory Select

bits need to be set to specify the memory for the operations. When 0, the Memory Select bits specify

the memory for subsequent operations. In either case, the Stream Address Bits select the subsection

of the memory which is made available.

6

ME

Message Enable. When 1, the contents of the Connection Memory Low are output on the Serial

Output streams except when in High Impedance. When 0, the Connection Memory bits for each

channel determine what is output.

4-3 MS1-MS0 Memory Select Bits. The memory select bits operate as follows:

0-0 - Not to be used

0-1 - Data Memory (read only from the CPU)

1-0 - Connection Memory Low

1-1 - Connection Memory High

2-0

STA2-0 Stream Address Bits 2-0. The number expressed in binary notation on these bits refers to the input

or output ST-BUS stream which corresponds to the subsection of memory made accessible for

subsequent operations.

Figure 4 - Control Register Bits

x = Don’t care

Initialization of the MT8985

On initialization or power up, the contents of the Connection Memory High can be in any state. This is a potentially

hazardous condition when multiple MT8985 ST-BUS outputs are tied together to form matrices, as these outputs

may conflict. The ODE pin should be held low on power up to keep all outputs in the high impedance condition.

8

Zarlink Semiconductor Inc.

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