MT8979 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc
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MT8979 Datasheet PDF : 34 Pages
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MT8979
Data Sheet
Control Output (CSTo)
Control ST-BUS output (CSTo) contains the multiframe signal from timeslot 16 of frame 0 (see Table 10). Signalling
bits A, B, C & D for each CEPT channel are sourced from timeslot 16 of frames 1-15 and are output in channels 1-
15 on CSTo , as shown in Table 11. The frame alignment signal and nonframe alignment signal, received from
timeslot 0 of alternate frames, are output in timeslots 16 and 17 as shown in Tables 12 and 13.
Channel 18 contains a Master Status Word, which provides to the user information needed to determine the
operating condition of the CEPT interface i.e., frame synchronization, multiframe synchronization, frame alignment
byte errors, slips, alarms, and the logic of the external status pin (see Table 14). Figure 12, shows the relationship
between the control stream channels and the CEPT signalling channels in the multiframe. The ERR bit in the
Master Status word is an indicator of the number of errored frame alignment bytes that have been received in
alternate timeslot zero. The time interval between toggles of the ERR bit can be used to evaluate the bit error rate
of the line according to the CCITT Recommendation G.732 (see section on Frame Alignment Error Counter).
Channel 19 contains the Phase Status Word (see Table 15), which can be used to determine the phase relationship
between the ST-BUS frame pulse (F0i) and the rising edge of E8Ko. This information could be used to determine
the long term trend of the received data rate, or to identify the direction of a slip.
Channel 20 contains the CRC error count (see Table 16). This counter will wrap around once terminal count is
achieved (256 errors). If the maintenance option is selected (bit 3 of MCW3) the counter is reset once per second.
Channel 21 contains the Master Status Word 2 (see Table 17). This byte identifies the status of the CRC reframe
and CRC sync. It also reports the Si bits received in timeslot 0 of frames 13 and 15 and the ninth and most
significant bit (b8) of the 9-bit Phase Status Word.
Elastic Buffer
The MT8979 has a two frame elastic buffer at the receiver, which absorbs the jitter and wander in the received
signal. The received data is written into the elastic buffer with the extracted E2i (2048 kHz) clock and read out of
the buffer on the ST-BUS side with the system C2i (2048 kHz) clock (e.g., PBX system clock). Under normal
operating conditions, in a synchronous network, the system C2i clock is phase-locked to the extracted E2i clock. In
this situation every write operation to the elastic buffer is followed by a read operation. Therefore, underflow or
overflow of data in the elastic buffer will not occur.
If the system clock is not phase-locked to the extracted clock (e.g., lower quality link which is not selected as the
clock source for the PBX) then the data rate at which the data is being written into the device on the line side may
differ from the rate at which it is being read out on the ST-BUS side.
When the clocks are not phase-locked, two situations can occur:
Case #1: If the data on the line side is being written in at a rate SLOWER than it is being read out on the ST-BUS
side, the distance between the write pointer and the read pointer will begin to decrease over time. When the
distance is less than two channels, the buffer will perform a controlled slip which will move the read pointers to a
new location 34 channels away from the write pointer. This will result in the REPETITION of the received frame.
Case #2: If the data on the line side is being written in at a rate FASTER than it is being read out on the ST-BUS
side, the distance between the write pointer and the read pointer will begin to increase over time. When the
distance exceeds 42 channels, the elastic buffer will perform a controlled slip which will move the read pointer to a
new location ten channels away from the write pointer. This will result in the LOSS of the last received frame.
Note that when the device performs a controlled slip, the ST-BUS address pointer is repositioned so that there is
either a 10 channel or 34 channel delay between the input CEPT frame and the output ST-BUS frame. Since the
buffer performs a controlled slip only if the delay exceeds 42 channels or is less than two channels, there is a
minimum eight channel hysteresis built into the slip mechanism. The device can, therefore, absorb eight channels
or 32.5 µs of jitter in the received signal.
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Zarlink Semiconductor Inc.
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