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MT8981D

ISO-CMOS ST-BUS FAMILY Digital Switch

Zarlink Semiconductor Inc 

MT8981D

Data Sheet

If bit 6 of the Control Register is 0, then bits 2 and 0 of each Connection Memory High location function normally

(see Fig. 5). If bit 2 is 1, the associated ST-BUS output channel is in Message Mode; i.e., the byte in the

corresponding Connection Memory Low location is transmitted on the stream at that channel. Otherwise, one of the

bytes received on the serial inputs is transmitted and the contents of the Connection Memory Low define the ST-

BUS input stream and channel where the byte is to be found (see Fig. 6).

If the ODE pin is low, then all serial outputs are high-impedance. If it is high and bit 6 in the Control Register is 1,

then all outputs are active. If the ODE pin is high and bit 6 in the Control Register is 0, then the bit 0 in the

Connection Memory High location enables the output drivers for the corresponding individual ST-BUS output

stream and channel. Bit 0=1 enables the driver and bit 0=0 disables it (see Fig. 5).

Applications

Use in a Simple Digital Switching System

Fig. 7 and 8 show how MT8981s can be used with MT8964s to form a simple digital switching system. Fig. 7 shows

the interface between the MT8981s and the filter/codecs. Fig. 8 shows the position of these components in an

example architecture.

The MT8964 filter/codec in Fig. 7 receives and transmits digitized voice signals on the ST-BUS input DR, and ST-

BUS output DX, respectively. These signals are routed to the ST-BUS inputs and outputs on the top MT8981, which

is used as a digital speech switch.

8981 used

as

speech

switch

STo0

STi0

MT8981

8981 used

in message

mode for

control and

signalling

STo0

STi0

MT8981

DX

DR

MT8964

Filter/Codec

DC

Signalling

Logic

Line Driver

and

2- to 4-

Wire

Converter

Line Interface Circuit with 8964 Filter/Codec

Figure 7 - Example of Typical Interface between 8981s and 8964s for Simple Digital Switching

System

The MT8964 is controlled by the ST-BUS input DC originating from the bottom MT8981, which generates the

appropriate signals from an output channel in Message Mode. This architecture optimizes the messaging capability

of the line circuit by building signalling logic, e.g., for on-off hook detection, which communicates on an ST-BUS

output. This signalling ST-BUS output is monitored by a microprocessor (not shown) through an ST-BUS input on

the bottom MT8981.

8

Zarlink Semiconductor Inc.

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