MT8981D 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc
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MT8981D Datasheet PDF : 20 Pages
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MT8981D
Data Sheet
STi3
7
IC 8
IC 9
IC 10
IC 11
VDD 12
F0i
13
C4i
14
A0 15
A1 16
A2 17
39 STo3
38 IC
37 IC
36 IC
35 IC
34 VSS
33 D0
32 D1
31 D2
30 D3
29 D4
44 PIN PLCC
DTA 1
STi0 2
STi1 3
STi2 4
STi3 5
IC 6
IC 7
IC 8
IC 9
VDD 10
F0i 11
C4i 12
A0 13
A1 14
A2 15
A3 16
A4 17
A5 18
DS 19
R/W 20
40 IC
39 ODE
38 STo0
37 STo1
36 STo2
35 STo3
34 IC
33 IC
32 IC
31 IC
30 VSS
29 D0
28 D1
27 D2
26 D3
25 D4
24 D5
23 D6
22 D7
21 CS
40 PIN PLASTIC DIP
Figure 2 - Pin Connections
Pin Description
Pin #
Name
40 44
DIP PLCC
Description
1 2 DTA Data Acknowledgement (Open Drain Output). This is the data acknowledgement on the
microprocessor interface. This pin is pulled low to signal that the chip has processed the data. A
909 Ω, 1/4 W, resistor is recommended to be used as a pullup.
2-4 3-5 STi0- ST-BUS Input 0 to 2 (Inputs). These are the inputs for the 2048 kbit/s ST-BUS input streams.
STi2
5 7 STi3 ST-BUS Input 3 (Input). These are the inputs for the 2048 kbit/s ST-BUS input streams.
6-9 8-11 IC Internal Connections. Must be connected to VDD.
10 12 VDD Power Input. Positive Supply.
11 13 F0i Framing 0-Type (Input). This is the input for the frame synchronization pulse for the 2048 kbit/s
ST-BUS streams. A low on this input causes the internal counter to reset on the next negative
transition of C4i.
12 14 C4i 4.096 MHz Clock (Input). ST-BUS bit cell boundaries lie on the alternate falling edges of this clock.
13-15 15-17 A0-A2 Address 0 to 2 (Inputs). These are the inputs for the address lines on the microprocessor interface.
16-18 19-21 A3-A5 Address 3 to 5 (Inputs). These are the inputs for the address lines on the microprocessor interface
19 22 DS Data Strobe (Input). This is the input for the active high data strobe on the microprocessor interface.
2
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