MT8980DP1 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc
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MT8980DP1 Datasheet PDF : 20 Pages
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MT8980D
Data Sheet
A5 A4 A3 A2 A1 A0 HEX ADDRESS
0
X
X
X
X
X
1
0
0
0
0
0
1
0
0
0
0
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
1
1
1
1
1
00 - 1F
20
21
•
•
•
3F
* Writing to the Control Register is the only fast transaction.
† Memory and stream are specified by the contents of the Control Register.
Figure 3 - Address Memory Map
LOCATION
Control Register *
Channel 0†
Channel 1†
•
•
•
Channel 31†
Software Control
The address lines on the Control Interface give access to the Control Register directly or, depending on the
contents of the Control Register, to the High or Low sections of the Connection Memory or to the Data Memory.
If address line A5 is low, then the Control Register is addressed regardless of the other address lines (see Fig. 3). If
A5 is high, then the address lines A4-A0 select the memory location corresponding to channel 0-31 for the memory
and stream selected in the Control Register.
The data in the Control Register consists of mode control bits, memory select bits, and stream address bits (see
Fig. 4). The memory select bits allow the Connection Memory High or Low or the Data Memory to be chosen, and
the stream address bits define one of the ST-BUS input or output streams.
5
Zarlink Semiconductor Inc.
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