MT8960 데이터 시트보기 (PDF) - Mitel Networks

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MT8960

Integrated PCM Filter Codec

Mitel Networks 

ISO2-CMOS MT8960/61/62/63/64/65/66/67

Powerdown

Powerdown of the chip is achieved in several ways:

Internal Control:

1) Initial Power-up. Initial application of VDD and

VEE causes powerdown for a period of 25 clock

cycles and during this period the chip will

accept input only from C2i. The B-register is

reset to zero forcing SD0-5 to be inactive. Bits

0-5 of Register A (gain adjust bits) are forced

to zero and bits 6 and 7 of Register A become

logic high thus reinforcing the powerdown.

2) Loss of C2i. Powerdown is entered 10 to 40

µs after C2i has assumed a continuous logic

high (VDD). In this condition the chip will be in

the same state as in (1) above.

Note: If C2i stops at a continuous logic low

(GNDD), the digital data and status is

indeterminate.

External Control:

1) Register A. Powerdown is controlled by bits 6

and 7 ( when both at logic high) of Register A

which in turn receives its control word input

via CSTi, when F1i is low and CA input is

either at VEE or GNDD. Power is removed

from the filters and analog sections of the chip.

The analog ouput buffer at VR will be

connected to GNDA. DSTo becomes high

impedance and the clocks to the majority of the

logic are stopped. SD outputs are unaffected

and may be updated as normal.

2) CSTi Input. With CA at VEE and CSTi held at

continuous logic high the chip assumes the

same state as described in External Control

(1) above.

From ST-BUS

From ST-BUS

Master Clock

to ST-BUS

5V

Alignment

Register Select

MT8960/61/64/65

CSTi

DSTi

C2i

DSTo

VDD

F1i

CA

SD3

SD2

GNDD

VRef

GNDA

VR

ANUL

VX

VEE

SD0

SD1

2.5V

0.1µF

-5V

Ring Trip

Filter

(With Relay

Drive)

Message

Waiting

(With Relay

Drive)

-100V DC

Gain

Section

2/4 Wire

Converter

Telephone

Line

Ring Feed

(With Relay

Drive)

-48V DC

-48V DC

90VRMS

Figure 7 - Typical Use of the Special Drive Outputs

6-27

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