MT8960 데이터 시트보기 (PDF) - Mitel Networks
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MT8960 Datasheet PDF : 22 Pages
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ISO2-CMOS MT8960/61/62/63/64/65/66/67
Note: For Modes 1 and 2, F1i must be at logic low
for one period of 3.9 µs, in each 125 µs cycle, when
PCM data is being input and output, and the control
word at CSTi enters Register A. For Mode 3, F1i
must be at a logic low for two periods of 3.9 µs, in
each 125 µs cycle. In the first period, CA must be at
GNDD or VEE, and in the second period CA must be
high (VDD).
Control Registers A, B
The contents of these registers control the filter/
codec functions as described in Tables 2 and 3.
Bit 7 of the registers is the MSB and is defined as the
first bit of the serial data stream input (corresponding
to the sign bit of the PCM word).
On initial power-up these registers are set to the
powerdown condition for a maximum of 25 clock
cycles. During this time it is impossible to change
the data in these registers.
Chip Testing
By enabling Register B with valid data (eight-bit
control word input to CSTi when F1i=GNDD and CA=
VCC) the chip testing mode can be entered. Bits 6
and 7 (most sign bits) define states for testing the
transmit filter, receive filter and the codec function.
The input in each case is VX input and the output in
each case is VR output. (See Table 3 for details.)
Loopback
Loopback of the filter/codec is controlled by the
control word entered into Register A. Bits 6 and 7
(most sign bits) provide either a digital or analog
loopback condition. Digital loopback is defined as
follows:
• PCM input data at DSTi is latched into the PCM
input register and the output of this register is
connected to the input of the 3-state PCM
output register.
• The digital input to the PCM digital-to-analog
decoder is disconnected, forced to zero (0).
• The output of the PCM encoder is disabled and
thus the encoded data is lost. The PCM output
at DSTo is determined by the PCM input data.
Analog loopback is defined as follows:
• PCM input data is latched, decoded and filtered
as normal but not output at VR.
TRANSMIT (A/D)
BIT 2 BIT 1 BIT 0 FILTER GAIN (dB)
0
0
0
0
0
0
1
+1
0
1
0
+2
0
1
1
+3
1
0
0
+4
1
0
1
+5
1
1
0
+6
1
1
1
+7
RECEIVE (D/A)
BIT 5 BIT 4 BIT 3 FILTER GAIN (dB)
0
0
0
0
0
0
1
-1
0
1
0
-2
0
1
1
-3
1
0
0
-4
1
0
1
-5
1
1
0
-6
1
1
1
-7
BIT 7 BIT 6
FUNCTION CONTROL
0
0
0
1
Normal operation
Digital Loopback
1
0
Analog Loopback
1
1
Powerdown
Table 2. Control States - Register A
• Analog output buffer at VR has its input shorted
to GNDA and disconnected from the receive
filter output.
• Analog input at VX is disconnected from the
transmit filter input.
• The receive filter output is connected to the
transmit filter input. Thus the decode signal is
fed back through the receive path and encoded
in the normal way. The analog output buffer at
VR is not tested by this configuration.
In both cases of loopback, DSTi is the input
and DSTo is the output.
6-25
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