MT8941B 데이터 시트보기 (PDF) - Mitel Networks
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MT8941B Datasheet PDF : 22 Pages
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CMOS MT8941B
AC Electrical Characteristics† - Voltages are with respect to ground (VSS) unless otherwise stated. (Refer to Figure 14)
Characteristics
Sym Min Typ‡ Max Units
Test Conditions
1 Master clocks input rise time
tr
10
ns
2 Master clocks input fall time
tf
10
ns
3 C Master clock period
L (12.352MHz)*
4
O
C
Master clock period
K (16.384MHz)*
5 S Duty Cycle of master clocks
For DPLL #1, while operating to
tP12 80.943 80.958 80.974 ns provide the T1 clock signal.
For DPLL #2, while operating to
tP16 61.023 61.035 61.046 ns provide the CEPT and ST-BUS
timing signals.
45
50
55
%
6 Lock-in Range DPLL #1
DPLL #2
-2.33
-1.69
+2.33
+1.69
With the Master frequency
Hz tolerance at ±32 ppm.
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
* Please review the section on "Jitter Performance and Lock-in Range".
tr
tf
Master clock
inputs
2.4 V
1.5 V
0.4 V
tP12 or tP16
Figure 17 - Master Clock Inputs
AC Electrical Characteristics†- Voltages are with respect to ground (VSS) unless otherwise stated. (Refer to Figure 18)
Characteristics
Sym Min Typ‡ Max Units
Test Conditions
1 F0b input pulse width (LOW)
tWFP
244
ns
2 C4b input clock period
tP4o
244
ns
3 Frame pulse (F0b) setup time
tFS
50
ns
4 Frame pulse (F0b) hold time
tFH
25
ns
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
VIH
F0b VIL
VIH
C4b VIL
tFS
tWFP
tFH
tP4o
Figure 18 - External Inputs on C4b and F0b for the DPLL #2
17
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