ML4821CP 데이터 시트보기 (PDF) - Micro Linear Corporation
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ML4821CP Datasheet PDF : 12 Pages
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ML4821
UNDER VOLTAGE LOCKOUT,
OVP AND CURRENT LIMIT
On power-up the ML4821 remains in the UVLO
condition; output low and quiescent current low. The IC
becomes operational when VCC reaches 16V. When VCC
drops below 9V, the UVLO condition is imposed. During
the UVLO condition, the VREF pin is “off”, making it
usable as a “flag” for starting up a down-stream PWM
converter.
OVP, SHUTDOWN, AND IC BIAS
When the input to the OVP comparator exceeds VREF, the
output of the ML4821 is inhibited. The OVP input also
functions as a “sleep” input, putting the IC into the low
quiescent UVLO state when the OVP pin is pulled below
0.7V.
500
RT = 5kΩ
VRMS = 3V
400
300
200
100
0
0
100
200
300
400
SINE INPUT CURRENT (µA)
5.5
4.5
3.5
2.5
1.5
1.0
500
Figure 7. Gain Modulator Linearity.
ENABLE
VREF
9V
INTERNAL
BIAS
4.4V
LOGIC
POWER
VREF 16
VCC 15
Figure 8. Under-Voltage Lockout Block Diagram.
40
30
20
TA = 25°C
10
0
0
10
20
30
VCC SUPPLY VOLTAGE (V)
Figure 9. Total Supply Current vs. Supply Voltage.
0
–4.0
–8.0
–12
–16
–20
–24
0
VCC = 15V
TA = 125°C
TA = –55°C
TA = 25°C
20
40
60
80
100
120
IREF, REFERENCE SOURCE CURRENT (mA)
Figure 10. Reference Load Regulation.
8
Micro Linear
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