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MK2049-02

Communications Clock PLLs

Integrated Circuit Systems 

MK2049-02/03

Communications Clock PLLs

OPERATING MODES (continued)

Loop Timing Mode

This mode can be used to remove the jitter from standard high-frequency communication clocks. For T1

and E1 inputs, the CLK1 output will be the same as the input frequency, with CLK2 at twice the input

frequency. For T3 and E3 inputs, CLK1 will be 1/2 the input frequency and CLK2 will be the same as the

input frequency.

Buffer Mode

Unlike the other two modes that accept only a single specified input frequency, Buffer Mode will accept a

wider range of input clocks. The input jitter is attenuated, and the outputs on CLK1 and CLK2 also

provide the option of getting x1, x2, x4, or 1/2 of the input frequency. For example, this mode can be used

to remove the jitter from a 27 MHz clock, generating low-jitter 27 MHz and 13.5 MHz outputs.

INPUT AND OUTPUT SYNCHRONIZATION

As shown in the tables on pages 4 and 5, the MK2049-02/03 offer a Zero Delay feature in most selections.

In these selections, there is an internal feedback path between ICLK and the CLK2 output clock. This

provides a fixed phase relationship between the input and output, a requirement in many communications

systems.

MK2049-02

As illustrated in the diagram below, when using the MK2049-02 in one of the Zero Delay selections, the

rising edge of ICLK will be aligned with the rising edge of CLK2. However, the CLK1 edge in these cases

will be either rising or falling. (8 kHz is used in this illustration, but the same is true for the Zero Delay

selections in the Loop Timing and Buffer modes.)

ICLK (8 kHz)

CLK2 (MHz)

CLK1 (MHz)

Figure 1. MK2049-02 Input and Output Clock Waveforms in Zero Delay Selections

MDS 2049-02/03 B

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Revision 040601

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