MK2049-02 데이터 시트보기 (PDF) - Integrated Circuit Systems
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MK2049-02 Datasheet PDF : 12 Pages
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Pin Assignment
FS1 1
X2 2
X1 3
VDD 4
VDD 5
VDD 6
GND 7
CLK2 8
CLK1 9
CLK3 10
20 FS0
19 RESET
18 CAP2
17 GND
16 CAP1
15 VDD
14 GND
13 ICLK
12 FS3
11 FS2
20 pin (300 mil) SOIC
MK2049-02/03
Communications Clock PLLs
Pin Descriptions
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Name
FS1
X2
X1
VDD
VDD
VDD
GND
CLK2
CLK1
CLK3
FS2
FS3
ICLK
GND
VDD
CAP1
GND
CAP2
RESET
FS0
Type Description
I Frequency Select 1. Determines CLK input/outputs per tables on pages 4 & 5.
XO Crystal connection. Connect to a MHz crystal as shown in the tables on pages 4 & 5.
XI Crystal connection. Connect to a MHz crystal as shown in the tables on pages 4 & 5.
P Connect to +5V.
P Connect to +5V.
P Connect to +5V.
P Connect to ground.
O Clock 2 output determined by status of FS3:0 per tables on pages 4 & 5.
O Clock 1 output determined by status of FS3:0 per tables on pages 4 & 5. Always 1/2 of CLK2.
O Clock 3 as shown in tables on pages 4 &5; typically recovered 8 kHz clock output.
I Frequency Select 2. Determines CLK input/outputs per tables on pages 4 & 5.
I Frequency Select 3. Determines CLK input/outputs per tables on pages 4 & 5.
I Input clock connection. Connect to 8 kHz backplane or MHz clock.
P Connect to ground.
P Connect to +5V.
LF Connect the loop filter ceramic capacitors and resistor between this pin and CAP2.
P Connect to ground.
LF Connect the loop filter ceramic capacitors and resistor between this pin and CAP1.
I Reset pin. Resets internal PLL when low. Outputs will stop low. Internal pull-up resistor.
I Frequency Select 0. Determines CLK input/outputs per tables on pages 4 & 5.
Type: XI, XO = crystal connections, I = Input, O = output, P = power supply connection, LF = loop filter
connections
MDS 2049-02/03 B
2
Revision 040601
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com
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