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MC74HCT373

Octal 3−State Noninverting Transparent Latch with LSTTL−Compatible Inputs

ON Semiconductor 

MC74HCT373A

LOGIC DIAGRAM

DATA

INPUTS

D0 3

D1 4

D2 7

D3 8

D4 13

D5 14

D6 17

D7 18

LATCH ENABLE 11

OUTPUT ENABLE 1

2 Q0

5 Q1

6 Q2

9 Q3

12 Q4

15 Q5

16 Q6

19 Q7

NONINVERTING

OUTPUTS

PIN 20 = VCC

PIN 10 = GND

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Design Criteria

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Internal Gate Count*

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Internal Gate Propagation Delay

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Internal Gate Power Dissipation

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Speed Power Product

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ *Equivalent to a two–input NAND gate.

Value

49

1.5

5.0

.0075

Units

ea.

ns

µW

pJ

PIN ASSIGNMENT

OUTPUT 1

ENABLE

Q0 2

D0 3

20 VCC

19 Q7

18 D7

D1 4

17 D6

Q1 5

Q2 6

D2 7

16 Q6

15 Q5

14 D5

D3 8

13 D4

Q3 9

GND 10

12 Q4

11 LATCH

ENABLE

FUNCTION TABLE

Inputs

Output

Output Latch

Enable Enable D

Q

L

H

H

H

L

H

L

L

L

L

X No Change

H

X

X

Z

X = don’t care

Z = high impedance

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