MC100E211 데이터 시트보기 (PDF) - ON Semiconductor

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MC100E211

5V ECL 1:6 Differential Clock Distribution Chip

ON Semiconductor 

MC10E211, MC100E211

APPLICATIONS INFORMATION

Differential versus Single−Ended Use

As can be seen from the data sheet, to minimize the skew

IN

of the E211 the device must be used in the differential mode.

In the single−ended mode the propagation delays are

dependent on the relative position of the VBB switching

reference. Any VBB offset from the center of the input swing

will add delay to either the TPLH or TPHL and subtract delay

from the other. This increase and decrease in delay will lead

to an increase in the duty cycle skew and thus part−to−part

skew. The within−device skew will be independent of the

VBB and therefore will be the same regardless of whether the

device is driven differentially or single−ended.

For applications where part−to−part skew or duty cycle

skew are not important the advantages of single−ended

clock distribution may lead to its use. Using single−ended

interconnect will reduce the number of signal traces to be

routed, but remember that all of the complementary outputs

still need to be terminated therefore there will be no

reduction in the termination components required. To use

the E211 with a single−ended input the arrangement pictured

in Figure 5 should be used. If the input to the differential

CLK inputs are AC coupled as pictured in Figure 4 the

dependence on a centered VBB reference is removed. The

situation pictured will ensure that the input is centered

around the bias set by the VBB. As a result when AC coupled

the AC specification limits for a differential input can be

used. For more information on AC coupling please refer to

the interfacing section of the design guide in the ECLinPS

data book.

Using the Enable Pins

Both the common enable (CEN) and the individual

enables (ENx) are synchronous to the CLK or SCLK input

depending on which is selected. The active low signals are

clocked into the enable flip flops on the negative edges of the

E211 clock inputs. In this way the devices will only be

disabled when the outputs are already in the LOW state. The

internal propagation delays are such that the delay to the

output through the distribution buffers is less than that

through the enable flip flops. This will ensure that the

disabling of the device will not slice any time off the clock

pulse. On initial power up the enable flip flops will randomly

attain a stable state, therefore precautions should be taken on

initial power up to ensure the E211 is in the desired state.

0.001mF

50 W

IN

0.01mF

VBB

Figure 4. AC Coupled Input

IN

IN

0.01 mF

VBB

Figure 5. Single−Ended Input

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