High-Current, 25Ω, SPDT, CMOS
Analog Switches
Test Circuits/Timing Diagrams
+3V
LOGIC
INPUT 0
VNC
SWITCH VO
OUTPUT
VNO
tR < 20ns
50%
tF < 20ns
tTRANS
tTRANS
0.9VNO 0.9VNC
Figure 2. Functional Diagram
MAX4659/MAX4660
V+
VNC
VNO
LOGIC
INPUT
NC V+
NO
IN
GND
COM
V-
V-
VO
RL
CL
300 Ω
35pF
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
MAX4659/MAX4660
V+
+3V
LOGIC
INPUT
V+
NC
COM
NO
IN
GND V-
V-
VOUT
RL
300Ω
CL
35pF
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
Figure 3. Break-Before-Make Time
+3V
LOGIC
INPUT
50%
0
SWITCH
OUTPUT
(VOUT)
0.9 ✕ VOUT
tBBM
∆VO
VO
IN
OFF
OFF
ON
Q = (∆VO)(CL)
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
Figure 4. Charge Injection
VGEN
COM
GND
V+ MAX4659/MAX4660
V+
NC OR
NO
V-
VO
CL
1nF
V-
VIN = +3V
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