MAX146ACAP(2001) 데이터 시트보기 (PDF) - Maxim Integrated

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MAX146ACAP
(Rev.:2001)

+2.7V, Low-Power, 8-Channel, Serial 12-Bit ADCs

Maxim Integrated 

+2.7V, Low-Power, 8-Channel,

Serial 12-Bit ADCs

Data Framing

The falling edge of CS does not start a conversion.

The first logic high clocked into DIN is interpreted as a

start bit and defines the first bit of the control byte. A

conversion starts on SCLK’s falling edge, after the eighth

bit of the control byte (the PD0 bit) is clocked into DIN.

The start bit is defined as follows:

The first high bit clocked into DIN with CS low any

time the converter is idle; e.g., after VDD is applied.

OR

The first high bit clocked into DIN after bit 5 of a con-

version in progress is clocked onto the DOUT pin.

If CS is toggled before the current conversion is com-

plete, the next high bit clocked into DIN is recognized as

a start bit; the current conversion is terminated, and a

new one is started.

The fastest the MAX146/MAX147 can run with CS held

low between conversions is 15 clocks per conversion.

Figure 11a shows the serial-interface timing necessary to

perform a conversion every 15 SCLK cycles in external

clock mode. If CS is tied low and SCLK is continuous,

guarantee a start bit by first clocking in 16 zeros.

Most microcontrollers (µCs) require that conversions

occur in multiples of 8 SCLK clocks; 16 clocks per con-

version is typically the fastest that a µC can drive the

MAX146/MAX147. Figure 11b shows the serial-

interface timing necessary to perform a conversion every

16 SCLK cycles in external clock mode.

Applications Information

Power-On Reset

When power is first applied, and if SHDN is not pulled

low, internal power-on reset circuitry activates the

MAX146/MAX147 in internal clock mode, ready to con-

vert with SSTRB = high. After the power supplies stabi-

lize, the internal reset time is 10µs, and no conversions

should be performed during this phase. SSTRB is high

on power-up and, if CS is low, the first logical 1 on DIN

is interpreted as a start bit. Until a conversion takes

place, DOUT shifts out zeros. (Also see Table 4.)

CS

SCLK

DIN

DOUT

SSTRB

1

8

15 1

8

15 1

S

CONTROL BYTE 0

S

CONTROL BYTE 1

B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

CONVERSION RESULT 0

S CONTROL BYTE 2

B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

CONVERSION RESULT 1

Figure 11a. External Clock Mode, 15 Clocks/Conversion Timing

CS

SCLK

DIN

DOUT

1

8

S CONTROL BYTE 0

16

1

8

S CONTROL BYTE 1

B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

CONVERSION RESULT 0

•••

16

•••

•••

B11 B10 B9 B8 • • •

CONVERSION RESULT 1

Figure 11b. External Clock Mode, 16 Clocks/Conversion Timing

______________________________________________________________________________________ 15

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