MAX146ACAP(2001) 데이터 시트보기 (PDF) - Maxim Integrated

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MAX146ACAP
(Rev.:2001)

+2.7V, Low-Power, 8-Channel, Serial 12-Bit ADCs

Maxim Integrated 

+2.7V, Low-Power, 8-Channel,

Serial 12-Bit ADCs

processor’s convenience, at any clock rate from 0MHz

to 2MHz. SSTRB goes low at the start of the conversion

and then goes high when the conversion is complete.

SSTRB is low for a maximum of 7.5µs (SHDN = FLOAT),

during which time SCLK should remain low for best

noise performance.

An internal register stores data when the conversion is

in progress. SCLK clocks the data out of this register at

any time after the conversion is complete. After SSTRB

goes high, the next falling clock edge produces the

MSB of the conversion at DOUT, followed by the

remaining bits in MSB-first format (Figure 9). CS does

not need to be held low once a conversion is started.

Pulling CS high prevents data from being clocked into

the MAX146/MAX147 and three-states DOUT, but it

does not adversely affect an internal clock mode

conversion already in progress. When internal clock

mode is selected, SSTRB does not go into a high-

impedance state when CS goes high.

Figure 10 shows the SSTRB timing in internal clock

mode. In this mode, data can be shifted in and out of

the MAX146/MAX147 at clock rates exceeding 2.0MHz

if the minimum acquisition time (tACQ) is kept above

1.5µs.

CS

SCLK

1 2 345678

9 10 11 12

DIN

SSTRB

DOUT

SEL2 SEL1 SEL0

UNI/

BIP

SGL/

DIF

PD1

PD0

START

tCONV

A/D STATE

ACQUISITION CONVERSION

IDLE

1.5µs

7.5µs MAX

(fSCLK = 2MHz) (SHDN = FLOAT)

Figure 9. Internal Clock Mode Timing

B11

MSB

B10

B9

IDLE

18 19 20 21 22 23 24

B2

B1

B0 FILLED WITH

LSB ZEROS

CS

tCONV

tCSH

tCSS

tSCK

SSTRB

SCLK

tSSTRB

tDO

PD0 CLOCK IN

DOUT

NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.

Figure 10. Internal Clock Mode SSTRB Detailed Timing

14 ______________________________________________________________________________________

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