MC80C86 데이터 시트보기 (PDF) - Intel

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MC80C86

16-BIT CHMOS MICROPROCESSOR

Intel 

M80C86 M80C86-2

WORKAROUND

A hardware workaround has been designed and

tested The workaround circuit (Figure 3) qualifies

the RD signal coming out of the M80C86 80C88

during valid read cycles and forces it to be inactive

otherwise (see the timing diagram in Figure 4) The-

delay in the RDM signal is limited to 6 ns (Max) by

using fast gate devices This should not have any

impact in the design since the RDM pulse width is

still the same as the orginal RD pulse width RDM is

also guaranteed to go inactive during the T4 state of

all read cycles

Figure 3

271058 – 18

Figure 4

271058 – 19

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