M38B50E1H-E107FP 데이터 시트보기 (PDF) - Mitsumi

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M38B50E1H-E107FP

8-BIT SINGLE-CHIP MICROCOMPUTER

Mitsumi 

HARDWARE

FUNCTIONAL DESCRIPTION

FUNCTIONAL DESCRIPTION

Central Processing Unit (CPU)

The 38B5 group uses the standard 740 Family instruction set. Re-

fer to the table of 740 Series addressing modes and machine

instructions or the 740 Series Software Manual for details on the

instruction set.

Machine-resident 740 Series instructions are as follows:

The FST and SLW instructions cannot be used.

The STP, WIT, MUL, and DIV instructions can be used.

[Accumulator (A)]

The accumulator is an 8-bit register. Data operations such as data

transfer, etc., are executed mainly through the accumulator.

[Index Register X (X)]

The index register X is an 8-bit register. In the index addressing

modes, the value of the OPERAND is added to the contents of

register X and specifies the real address.

[Index Register Y (Y)]

The index register Y is an 8-bit register. In partial instruction, the

value of the OPERAND is added to the contents of register Y and

specifies the real address.

[Stack Pointer (S)]

The stack pointer is an 8-bit register used during subroutine calls

and interrupts. This register indicates start address of stored area

(stack) for storing registers during subroutine calls and interrupts.

The low-order 8 bits of the stack address are determined by the

contents of the stack pointer. The high-order 8 bits of the stack ad-

dress are determined by the stack page selection bit. If the stack

page selection bit is “0” , the high-order 8 bits becomes “0016”. If

the stack page selection bit is “1”, the high-order 8 bits becomes

“0116”.

The operations of pushing register contents onto the stack and

popping them from the stack are shown in Figure 6.

Store registers other than those described in Figure 6 with pro-

gram when the user needs them during interrupts or subroutine

calls.

[Program Counter (PC)]

The program counter is a 16-bit counter consisting of two 8-bit

registers PCH and PCL. It is used to indicate the address of the

next instruction to be executed.

b15

PCH

b7

b0

A

Accumulator

b7

b0

X

Index register X

b7

b0

Y

Index register Y

b7

b0

S

Stack pointer

b7

b0

PCL

Program counter

b7

b0

N V T B D I Z C Processor status register (PS)

Carry flag

Zero flag

Interrupt disable flag

Decimal mode flag

Break flag

Index X mode flag

Overflow flag

Negative flag

Fig. 5 740 Family CPU register structure

1-8

38B5 Group User’s Manual

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