M38B50E1H-E107FP 데이터 시트보기 (PDF) - Mitsumi

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M38B50E1H-E107FP

8-BIT SINGLE-CHIP MICROCOMPUTER

Mitsumi 

List of figures

Fig. 2.3.22 Registers setting relevant to transmission side ................................................... 2-51

Fig. 2.3.23 Setting of transmission data ................................................................................... 2-51

Fig. 2.3.24 Control procedure..................................................................................................... 2-52

Fig. 2.3.25 Connection diagram ................................................................................................. 2-53

Fig. 2.3.26 Timing chart of serial data transmission/reception .............................................. 2-53

Fig. 2.3.27 Relevant registers setting ....................................................................................... 2-54

Fig. 2.3.28 Control procedure ..................................................................................................... 2-55

Fig. 2.3.29 Serial I/O2 connection examples (1) ..................................................................... 2-56

Fig. 2.3.30 Serial I/O2 connection examples (2) ..................................................................... 2-57

Fig. 2.3.31 Serial I/O2’s modes ................................................................................................. 2-58

Fig. 2.3.32 Serial I/O2 transfer data format ............................................................................. 2-58

Fig. 2.3.33 Connection diagram ................................................................................................. 2-59

Fig. 2.3.34 Timing chart .............................................................................................................. 2-59

Fig. 2.3.35 Registers setting relevant to transmission side ................................................... 2-60

Fig. 2.3.36 Registers setting relevant to reception side......................................................... 2-61

Fig. 2.3.37 Control procedure of transmission side ................................................................ 2-62

Fig. 2.3.38 Control procedure of reception side ...................................................................... 2-63

Fig. 2.3.39 Connection diagram ................................................................................................. 2-64

Fig. 2.3.40 Timing chart .............................................................................................................. 2-64

Fig. 2.3.41 Relevant registers setting ....................................................................................... 2-65

Fig. 2.3.42 Setting of transmission data ................................................................................... 2-65

Fig. 2.3.43 Control procedure..................................................................................................... 2-66

Fig. 2.3.44 Connection diagram ................................................................................................. 2-67

Fig. 2.3.45 Timing chart .............................................................................................................. 2-68

Fig. 2.3.46 Relevant registers setting in master unit .............................................................. 2-68

Fig. 2.3.47 Relevant registers setting in slave unit ................................................................ 2-69

Fig. 2.3.48 Control procedure of master unit ........................................................................... 2-70

Fig. 2.3.49 Control procedure of slave unit ............................................................................. 2-71

Fig. 2.3.50 Connection diagram ................................................................................................. 2-72

Fig. 2.3.51 Timing chart .............................................................................................................. 2-72

Fig. 2.3.52 Registers setting relevant to transmission side ................................................... 2-74

Fig. 2.3.53 Registers setting relevant to reception side......................................................... 2-75

Fig. 2.3.54 Control procedure of transmission side ................................................................ 2-76

Fig. 2.3.55 Control procedure of reception side ...................................................................... 2-77

Fig. 2.3.56 Sequence of setting serial I/O2 control register again ....................................... 2-81

Fig. 2.4.1 Memory assignment of FLD controller relevant registers ..................................... 2-83

Fig. 2.4.2 Structure of P1FLDRAM write disable register ...................................................... 2-84

Fig. 2.4.3 Structure of P3FLDRAM write disable register ...................................................... 2-85

Fig. 2.4.4 Structure of FLD mode register ............................................................................... 2-86

Fig. 2.4.5 Structure of Tdisp time set register ......................................................................... 2-87

Fig. 2.4.6 Structure of Toff1 time set register ......................................................................... 2-88

Fig. 2.4.7 Structure of Toff2 time set register ......................................................................... 2-88

Fig. 2.4.8 Structure of FLD data pointer/FLD data pointer reload register ......................... 2-89

Fig. 2.4.9 Structure of port P0FLD/port switch register .......................................................... 2-89

Fig. 2.4.10 Structure of port P2FLD/port switch register ....................................................... 2-90

Fig. 2.4.11 Structure of port P8FLD/port switch register ....................................................... 2-90

Fig. 2.4.12 Structure of port P8FLD output control register .................................................. 2-91

Fig. 2.4.13 Structure of interrupt request register 2 ............................................................... 2-91

Fig. 2.4.14 Structure of interrupt control register 2 ................................................................ 2-92

Fig. 2.4.15 Connection diagram ................................................................................................. 2-93

Fig. 2.4.16 Timing chart of key-scan using FLD automatic display mode and segments. 2-93

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38B5 Group User’s Manual

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