M24C32MN5T 데이터 시트보기 (PDF) - STMicroelectronics
부품명
상세내역
일치하는 목록
M24C32MN5T Datasheet PDF : 26 Pages
| |||
M24C64, M24C32
Table 16. AC Characteristics (M24Cxx-6, M24Cxx-W6 and M24Cxx-W3)
Test conditions specified in Table 11. and Table 8. or Table 9.
Symbol
Alt.
Parameter
Min.
Max.
Unit
fC
fSCL Clock Frequency
400
kHz
tCHCL
tHIGH Clock Pulse Width High
600
ns
tCLCH
tLOW Clock Pulse Width Low
1300
ns
tDL1DL2 2
tF
SDA Fall Time
20
300
ns
tDXCX
tSU:DAT Data In Set Up Time
100
ns
tCLDX
tHD:DAT Data In Hold Time
0
ns
tCLQX
tDH
Data Out Hold Time
200
ns
tCLQV 3
tAA
Clock Low to Next Data Valid (Access Time)
200
900
ns
tCHDX 1
tSU:STA Start Condition Set Up Time
600
ns
tDLCL
tHD:STA Start Condition Hold Time
600
ns
tCHDH
tSU:STO Stop Condition Set Up Time
600
ns
tDHDL
tBUF Time between Stop Condition and Next Start Condition
1300
ns
tW
tWR
Write Time
5 or4 10
ms
Note: 1. For a reSTART condition, or following a Write cycle.
2. Sampled only, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
4. The Write Time of 5 ms only applies to devices bearing the process letter “B” in the package marking (on the top side of the pack-
age), otherwise (for devices bearing the process letter “N”) the Write Time is 10 ms. For further details, please contact your nearest
ST sales office, and ask for a copy of the Product Change Notice PCEE0036.
Table 17. AC Characteristics (M24Cxx-R)
Test conditions specified in Table 11. and Table 10.
Symbol
Alt.
Parameter
Min.
Max.
Unit
fC
fSCL Clock Frequency
400
kHz
tCHCL
tHIGH Clock Pulse Width High
600
ns
tCLCH
tLOW Clock Pulse Width Low
1300
ns
tDL1DL2 2
tF
SDA Fall Time
20
300
ns
tDXCX
tSU:DAT Data In Set Up Time
100
ns
tCLDX
tHD:DAT Data In Hold Time
0
ns
tCLQX
tDH
Data Out Hold Time
200
ns
tCLQV 3
tAA
Clock Low to Next Data Valid (Access Time)
200
900
ns
tCHDX 1
tSU:STA Start Condition Set Up Time
600
ns
tDLCL
tHD:STA Start Condition Hold Time
600
ns
tCHDH
tSU:STO Stop Condition Set Up Time
600
ns
tDHDL
tBUF Time between Stop Condition and Next Start Condition
1300
ns
tW
tWR
Write Time
10
ms
Note: 1. For a reSTART condition, or following a Write cycle.
2. Sampled only, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
18/26
Share Link: 