M24C32MN5T 데이터 시트보기 (PDF) - STMicroelectronics

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M24C32MN5T

64Kbit and 32Kbit Serial I²C Bus EEPROM

STMicroelectronics 

M24C64, M24C32

Sequential Read

This operation can be used after a Current Ad-

dress Read or a Random Address Read. The bus

master does acknowledge the data byte output,

and sends additional clock pulses so that the de-

vice continues to output the next byte in sequence.

To terminate the stream of bytes, the bus master

must not acknowledge the last byte, and must

generate a Stop condition, as shown in Figure 10..

The output data comes from consecutive address-

es, with the internal address counter automatically

incremented after each byte output. After the last

memory address, the address counter ‘rolls-over’,

and the device continues to output data from

memory address 00h.

Acknowledge in Read Mode

For all Read commands, the device waits, after

each byte read, for an acknowledgment during the

9th bit time. If the bus master does not drive Serial

Data (SDA) Low during this time, the device termi-

nates the data transfer and switches to its Stand-

by mode.

INITIAL DELIVERY STATE

The device is delivered with all bits in the memory

array set to 1 (each byte contains FFh).

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