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PCK2510S

50-150 MHz 110 SDRAM clock driver

Philips Electronics 

Philips Semiconductors

50–150 MHz 1:10 SDRAM clock driver

Product specification

PCK2510S

SWITCHING CHARACTERISTICS

Over recommended ranges of supply voltage and operating free-air temperature; CL = 30 pF1

PARAMETER

FROM

(INPUT)/CONDITION

TO

(OUTPUT)

tphase error 2

tphase error – jitter 3

tSK(0)

jitter(peak-peak)

jitter (cycle-cycle)

Duty cycle reference

CLKIN↑ = 100 MHz to 133 MHz

CLKIN↑ = 66 MHz

CLKIN↑ = 100 MHz to 133 MHz

Any Y or FBOUT

CLKIN = 100 MHz to 133 MHz

F(CLKIN > 60 MHz)

FBIN↑

FBIN↑

FBIN↑

Any Y or FBOUT

Any Y or FBOUT

Any Y or FBOUT

tr

VO = 0.4 V to 2 V

Any Y or FBOUT

tf

VO = 0.4 V to 2 V

Any Y or FBOUT

NOTES:

1. These parameters are not production tested.

2. This is considered as static phase error.

3. Phase error does not include jitter. (tphase error = static phase error – jitter(cycle-cycle))

4. The tSK(0) specification is only valid for equal loading of all outputs.

VCC, AVCC = 3.3 V ±0.3 V

MIN

TYP

MAX

–100

100

–125

125

–50

50

200

–80

80

|65|

47

53

2.5

1

2.5

1

UNIT

ps

ps

ps

ps

ps

%

V/ns

V/ns

PARAMETER MEASUREMENT INFORMATION

FROM OUTPUT

UNDER TEST

30pF

500Ω

LOAD CIRCUIT FOR OUTPUTS

3V

INPUT

50% VCC

0V

tpe

OUTPUT

2V

0.4V

tr

50% VCC

2V

VOH

0.4V VOL

tf

VOLTAGE WAVEFORMS & PHASE ERROR TIMES

NOTES:

1. CL includes probe and jig capacitance.

2. All input pulses are supplied by generators having the following characteristics: PRR ≤ 100MHz, ZO = 50Ω , tr ≤ 1.2ns, tf ≤ 1.2ns.

3. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms

SW00384

1999 Dec 13

6

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