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PCK2510S

50-150 MHz 110 SDRAM clock driver

Philips Electronics 

Philips Semiconductors

50–150 MHz 1:10 SDRAM clock driver

Product specification

PCK2510S

FUNCTIONAL BLOCK DIAGRAM

11

G

3

1Y0

4

1Y1

5 1Y2

8

1Y3

9 1Y4

CLK 24

PLL

FBIN 13

AVCC 23

15 1Y5

16 1Y6

17 1Y7

20

1Y8

21 1Y9

12 FBOUT

SW00383

ABSOLUTE MAXIMUM RATINGS 1, 3

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL

PARAMETER

CONDITION

LIMITS

MIN

MAX

UNIT

AVCC

Supply voltage range

Note 2

< VCC + 0.7

V

VCC

Supply voltage range

–0.5

+4.6

V

IIK

Input clamp current

VI < 0

–50

mA

VI

Input voltage range

Note 3

–0.5

6.5

V

IOK

Output clamp current

VO > VCC or VO < 0

±50

mA

VO

Output voltage range

Notes 3, 4

–0.5

VCC + 0.5

V

IO

DC output source or sink current

VO = 0 to VCC

±50

mA

TSTG

Storage temperature range

–65

+150

°C

PTOT

Power dissipation per package

700

mW

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the

device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to

absolute-maximum-rated conditions for extended periods may affect device reliability.

2. AVCC must not exceed VCC

3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

4. This value is limited to 4.6 V maximum.

1999 Dec 13

4

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