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SAA4963

Integrated NTSC comb filter

Philips Electronics 

Philips Semiconductors

Integrated NTSC comb filter

Preliminary specification

SAA4963

The PLL provides a master clock MCK of 6 × fsc, which is

locked to the subcarrier frequency at FSC (pin 1).

The system clock CL3 (3 × fsc) is obtained from MCK by a

divide-by-two circuit. The 180° phase shift is generated by

stopping the divide-by-two circuit for one MCK clock cycle.

The generated clock is a pseudo-line-locked clock that is

referenced to fsc. The sync separator generates the

necessary signals HDET and VDET indicating the line (H)

and the field (V) sync periods.

The input signals of the control and clock processing

(CLOCK CONTROL) are:

HDET: analog horizontal pulse from sync separator

VDET: analog vertical pulse from sync separator

FSC: subcarrier frequency

SVHS: SVHS control signal.

The output signals are:

CL3: system clock (3 × fsc)

HSEL: line start signal for the delay line

STOPS: forces the IC via the switches S2A and S2B into

the SVHS-mode or into COMB-mode (always

asynchronous).

HORIZONTAL AND VERTICAL SYNC SEPARATOR

A built-in sync separator circuit generates the HDET and

VDET signals from the CVBS input signal. This circuit is still

working properly with a 12 dB attenuated sync in a normal

700 mV black-to-white video input signal (see Fig.5).

Table 4 Function of pre clamp and main clamp

INPUT

CVBS

Yext

COMB-MODE

main clamp

pre clamp

SVHS-MODE

pre clamp

main clamp

SIGNAL SWITCHES S2A AND S2B

Two switches are included to bypass the comb filter signal

processing. The input video signal Cext for the switch S2B

is internally biased.

For the YO output two signals can be selected via S2A.

Table 5 YO output signal

SVHS

LOW

HIGH

YO OUTPUT SIGNAL

YCOMB (combed luminance)

input Yext

MODE

COMB

SVHS

For the CO output two signals can be selected via S2B.

Table 6 CO output signal

SVHS

LOW

HIGH

CO OUTPUT SIGNAL

CCOMB (combed chrominance)

input Cext

MODE

COMB

SVHS

CLAMP

The black level clamping of the video input signals (CVBS

and Yext) is performed by the sync separator stage.

The clamping level is nearly adequate to the voltage at

REFDL (pin 10). The clamp consists of a pre clamp and a

main clamp. Always the signal which is switched to the

output is clamped via the main clamp while the other signal

is pre clamped. This reduces the distortion during

switching from COMB-mode to SVHS-mode and vice

versa.

1997 Mar 03

7

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