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SAA4963

Integrated NTSC comb filter

Philips Electronics 

Philips Semiconductors

Integrated NTSC comb filter

Preliminary specification

SAA4963

CSY (PIN 12)

Sync top capacitor for the sync separator.

CVBS (PIN 13)

Input for the CVBS signal in COMB-mode.

YEXT (PIN 14)

Input for an external luminance signal in SVHS-mode.

REFBP (PIN 20)

Decoupling capacitor for the band-pass filter reference

voltage.

Internal functional description

SWITCHED CAPACITOR DELAY LINE

Delays the CVBS input signal by 1 line. Input signals for

the delay lines are the CVBS signal, the clock CL3 (3 × fsc)

and the control signal HSEL.

Output signals are the non-delayed and the 1-line delayed

CVBS signal.

SWITCHED CAPACITOR BAND-PASS FILTERS (BPFS)

The comb filter input BPFs attenuate the low frequencies

to guarantee a correct signal processing within the

comb filter.

The comb filter output BPF reduces the alias components

that are the result of the signal processing within the

comb filter.

CHROMINANCE COMB FILTER

Separates the chrominance from the band-pass filtered

CVBS signal.

DELAY COMPENSATION

Compensates the internal processing time of the

band-pass filters and the chrominance comb filter section.

LUMINANCE COMB FILTER

The comb filtered luminance output signal is obtained by

adding the delayed CVBS signal and the inverted comb

filtered chrominance signal.

LOW-PASS FILTER INPUT (LPFI)

Analog input low-pass filter to reduce the outband

frequencies of EMC. The input low-pass filter is included in

the signal path.

LOW-PASS FILTER OUTPUTS (LPFO1 AND LPFO2)

Two different types of output low-pass filters LPFO1 and

LPFO2 are necessary to get equal signal delays within the

luminance path and the chrominance path (important for

good transient behaviour). The low-pass output filter type

LPFO1 is used for the luminance output while LPFO2 is

used for the chrominance output. The filters are analog 3rd

order elliptic low-pass filters that convert the output signals

from the time discrete to the time continuous domain

(reconstruction filter).

LPF CONTROL

Automatic tuning of the low-pass filters is achieved by

adjusting the filter delays. The control information for all

filters (CONT1 and CONT2) is derived from a built-in

reference filter (LPFO1-type) that is part of a control loop.

The control loop tunes the reference filter delay and thus

all other filter delays to a time reference derived from the

system clock CL3.

CONTROL AND CLOCK PROCESSING (CLOCK CONTROL)

The control and clock processing block consists of the

sub-blocks PLL, clock processing and mode control. Only

if the input level at SVHS (pin 2) selects the COMB mode

the PLL and the clock processing are released for

operation.

Main tasks of the control and clock processing are:

• Clock generation of system clock CL3

• Delay line start control

• Mode control.

The signal processing is based on a 3 × fsc system clock

(CL3), that is generated by the clock processing from the

fsc-signal at FSC (pin 1) via a PLL. A clock phase

correction of 180° is necessary every line because the

subcarrier frequency divided by the line frequency results

not in an integer value. Additionally the clock processing is

synchronized fieldwise by the H-signal (correction of line

frequency instabilities).

1997 Mar 03

6

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