C3225X7R1E106M 데이터 시트보기 (PDF) - Intersil
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C3225X7R1E106M Datasheet PDF : 20 Pages
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ISL97650B
Pin Descriptions
PIN NUMBER
PIN NAME
DESCRIPTION
1
2
3
4
5, 18
6
7
8
9
10
11
12
13
14
LX1
LX2
CB
LXL
NC
VSUP
FBL
CM2
CTL
AGND2
DRN
COM
POUT
C1-
Internal boost switch connection
Internal boost switch connection
Logic buck, boost strap pin
Buck converter output
No connect. Connect to die pad and GND for improved thermal efficiency.
Positive supply for charge pumps
Logic buck feedback pin
Buck compensation network pin
Input control for VON slice output
Signal GND pin
Lower reference voltage for VON slice output
VON slice output: when CTL = 1, COM is connected to SRC through a 5Ω resistor; when CTL = 0, COM
is connected to DRN through a 30Ω resistor
Positive charge pump out
Charge pump capacitor 1, negative connection
15
C1+
Charge pump capacitor 1, positive connection
16
C2-
Charge pump capacitor 2, negative connection
17
19
20
21
22
23
24
25, 26
27
C2+
Charge pump capacitor 2, positive connection
FBP
Positive charge pump feedback pin
VREF
Reference voltage
FBN
Negative charge pump feedback pin
PGND3
NOUT
Power ground for VOFF, VON and VON slice
Negative charge pump output
VINL
Logic buck supply voltage
PGND2, PGND1 Boost Power grounds
AGND1
Signal ground pin
28
VDC1
Internal supply decoupling capacitor
29
CDEL
Delay capacitor for start up sequencing, soft-start and fault detection timers
30
ENL
Buck enable for VLOGIC output
31
DELB
Open drain NFET output to drive optional AVDD delay PFET
32
CM1
Boost compensation network pin
33
VIN
Input voltage pin
34
FBB
Boost feedback pin
35
EN
Enable for Boost, charge pumps and VON slice (independent of ENL)
36
VDC2
Internal supply decoupling capacitor
Thermal Pad
N/A
Connect exposed die plate on rear of package to ACGND and the PGND1, 2 pins. See “Layout
Recommendation” on page 19 for PCB layout thermal considerations.
8
FN6748.1
March 22, 2010
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