ISL97650 데이터 시트보기 (PDF) - Intersil
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ISL97650 Datasheet PDF : 20 Pages
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ISL97650
Pin Descriptions
PIN NUMBER
1
2
3
4
PIN NAME
LX1
LX2
CB
LXL
5, 18
6
7
8
9
10
11
12
NC
VSUP
FBL
CM2
CTL
AGND2
DRN
COM
13
14
15
16
17
19
20
21
22
23
24
25, 26
27
28
29
30
31
32
33
34
35
36
Exposed Die Plate
POUT
C1-
C1+
C2-
C2+
FBP
VREF
FBN
PGND3
NOUT
VINL
PGND2, 1
AGND1
VDC1
CDEL
ENL
DELB
CM1
VIN
FBB
EN
VDC2
N/A
DESCRIPTION
Internal boost switch connection
Internal boost switch connection
Logic buck, boost strap pin
Buck converter output
No connect. Connect to die pad and GND for improved thermal efficiency.
Positive supply for charge pumps
Logic buck feedback pin
Buck compensation network pin
Input control for VON slice output
Signal GND pin
Lower reference voltage for VON slice output
VON slice output: when CTL = 1, COM is connected to SRC through a 5Ω resistor; when CTL = 0, COM
is connected to DRN through a 30Ω resistor
Positive charge pump out
Charge pump capacitor 1, negative connection
Charge pump capacitor 1, positive connection
Charge pump capacitor 2, negative connection
Charge pump capacitor 2, positive connection
Positive charge pump feedback pin
Reference voltage
Negative charge pump feedback pin
Power ground for VOFF, VON and VON slice
Negative charge pump output
Logic buck supply voltage
Boost power grounds
Signal ground pin
Internal supply decoupling capacitor
Delay capacitor for start up sequencing, soft-start and fault detection timers
Buck enable for VLOGIC output
Open drain NFET output to drive optional AVDD delay PFET
Boost compensation network pin
Input voltage pin
Boost feedback pin
Enable for boost, charge pumps and VON slice (independent of ENL)
Internal supply decoupling capacitor
Connect exposed die plate on rear of package to ACGND and the PGND1, 2 pins. See the section on
"“Layout Recommendation” on page 19" for PCB layout thermal considerations.
8
FN9198.4
April 17, 2009
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