IP2004 데이터 시트보기 (PDF) - International Rectifier

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IP2004

SYNCHRONOUS BUCK LGA POWER BLOCK

International Rectifier 

Data Sheet No. PD60322

iP2004

Internal Block Diagram

VSWS1 VSWS2

8

9

NC 1

7 VIN

ENABLE 2

PWM 3

VDD 4

MOSFET

Driver with

dead time

control

5 VSW

PGND 10

6

PGND

Pin Description

Pin Number Pin Name

1

NC

2

ENABLE

3

4

5

6, 10

7

8

9

PWM

VDD

VSW

PGND

VIN

VSWS1

VSWS2

Figure 12 Internal Block Diagram

Description

No Connect. This pin is not for electrical connection

When set to logic level high, internal circuitry of the device is enabled. When

set to logic level low, the Control and Synchronous FETs are turned off.

TTL level input to MOSFET drivers. When PWM is HIGH, the Control FET is

on and the Sync FET is off. When PWM is LOW, the Sync FET is on and the

Control FET is off.

Supply voltage to internal circuitry.

Voltage Switching Node – pin connection to the output inductor.

Power Ground

Input voltage pin. Connect input capacitors close to this pin.

Floating pin. Externally connect to VSWS2 only.

Floating pin. Externally short to VSWS1 only.

Page 9 of 15

www.irf.com

12/22/2007

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