IMX51A 데이터 시트보기 (PDF) - Freescale Semiconductor

부품명

상세내역

일치하는 목록

IMX51A

i.MX51A Automotive and Infotainment Applications Processors

Freescale Semiconductor 

Features

Table 3. Special Signal Considerations (continued)

Signal Name

Remarks

IOB, IOG, IOR, IOB_BACK, These signals are analog TV outputs that should be tied to GND when not being used.

IOG_BACK, and

IOR_BACK

JTAG_nnnn

The JTAG interface is summarized in Table 4. Use of external resistors is unnecessary. However,

if external resistors are used, the user must ensure that the on-chip pull-up/down configuration is

followed. For example, do not use an external pull down on an input that has on-chip pull-up.

JTAG_TDO is configured with a keeper circuit such that the floating condition is eliminated if an

external pull resistor is not present. An external pull resistor on JTAG_TDO is detrimental and

should be avoided.

JTAG_MOD is referenced as SJC_MOD in the i.MX51 Reference Manual. Both names refer to the

same signal. JTAG_MOD must be externally connected to GND for normal operation. Termination

to GND through an external pull-down resistor (such as 1 kΩ) is allowed.

NC

These signals are No Connect (NC) and should be floated by the user.

PMIC_INT_REQ

When using the MC13892 power management IC, the PMIC_INT_REQ high-priority interrupt input

on i.MX51 should be either floated or tied to NVCC_SRTC_POW with a 4.7 kΩ to 68 kΩ resistor.

This avoids a continuous current drain on the real-time clock backup battery due to a 100 kΩ

on-chip pull-up resistor.

PMIC_INT_REQ is not used by the Freescale BSP (board support package) software. The BSP

requires that the general-purpose INT output from the MC13892 be connected to i.MX51 GPIO

input GPIO1_8 configured to cause an interrupt that is not high-priority.

The original intent was for PMIC_INT_REQ to be connected to a circuit that detects when the

battery is almost depleted. In this case, the I/O must be configured as alternate mode 0 (ALT0 =

power fail).

POR_B

This cold reset negative logic input resets all modules and logic in the IC.

Note: The POR_B input must be immediately asserted at power-up and remain asserted until

after the last power rail is at its working voltage.

RESET_IN_B

RREFEXT

This warm reset negative logic input resets all modules and logic except for the following:

• Test logic (JTAG, IOMUXC, DAP)

• SRTC

• Memory repair – Configuration of memory repair per fuse settings

• Cold reset logic of WDOG – Some WDOG logic is only reset by POR_B. See WDOG chapter

in i.MX51 Reference Manual for details.

Determines the reference current for the USB PHY bandgap reference. An external 6.04 kΩ 1%

resistor to GND is required.

SGND, SVCC, and

SVDDGP

STR

These sense lines provide the ability to sense actual on-chip voltage levels on their respective

supplies. SGND monitors differentials of the on-chip ground versus an external power source.

SVCC monitors on-chip VCC, and SVDDGP monitors VDDGP. Freescale recommends connection

of the SVCC and SVDDGP signals to the feedback inputs of switching power-supplies or to test

points.

This signal is reserved for Freescale manufacturing use. The user should float this signal.

TEST_MODE

TEST_MODE is for Freescale factory use only. This signal is internally connected to an on-chip

pull-down device. Users must either float this signal or tie it to GND.

i.MX51A Automotive and Infotainment Applications Processors, Rev. 2

12

Freescale Semiconductor

Preliminary—Subject to Change Without Notice

Share Link: