IDT72V845 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT72V845

3.3 VOLT CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18 and DUAL 4,096 x 18

Integrated Device Technology 

IDT72V805/72V815/72V825/72V835/72V845

3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

DESCRIPTION (CONTINUED)

FIFOs are applicable for a wide variety of data buffering needs, such as

optical disk controllers, Local Area Networks (LANs), and interprocessor

communication.

Each of the two FIFOs contained in these devices has an 18-bit input

and output port. Each input port is controlled by a free-running clock

(WCLK), and an input enable pin (WEN). Data is read into the synchronous

FIFO on every clock when WEN is asserted. The output port of each FIFO

bank is controlled by another clock pin (RCLK) and another enable pin

(REN). The Read Clock can be tied to the Write Clock for single clock

operation or the two clocks can run asynchronous of one another for dual-

clock operation. An Output Enable pin (OE) is provided on the read port

of each FIFO for three-state control of the output.

The synchronous FIFOs have two fixed flags, Empty Flag/Output Ready

(EF/OR) and Full Flag/Input Ready (FF/IR), and two programmable flags,

Almost-Empty (PAE) and Almost-Full (PAF). The offset loading of the

programmable flags is controlled by a simple state machine, and is initiated

by asserting the Load pin (LD). A Half-Full flag (HF) is available for each

FIFO that is implemented as a single device.

There are two possible timing modes of operation with these devices:

IDT Standard mode and First Word Fall Through (FWFT) mode.

In IDT Standard Mode, the first word written to an empty FIFO will not

appear on the data output lines unless a specific read operation is

performed. A read operation, which consists of activating REN and

enabling a rising RCLK edge, will shift the word from internal memory to the

data output lines.

In FWFT mode, the first word written to an empty FIFO is clocked directly

to the data output lines after three transitions of the RCLK signal. A REN

does not have to be asserted for accessing the first word.

These devices are depth expandable using a Daisy-Chain technique or

First Word Fall Through (FWFT) mode. The XI and XO pins are used to

expand the FIFOs. In depth expansion configuration, FL is grounded on

the first device and set to HIGH for all other devices in the Daisy Chain.

The IDT72V805/72V815/72V825/72V835/72V845 are fabricated using

IDT’s high-speed submicron CMOS technology.

PIN CONFIGURATIONS

INDEX

VCC

1

PAFA

2

RXIA

3

FFA

4

WXOA/HFA

5

RXOA

6

QA0

7

QA1

8

GND

9

QA2

10

QA3

11

VCC

12

QA4

13

GND

14

QA5

15

QA6

16

QA7

17

QA8

18

GND

19

DB7

20

DB6

21

DB5

22

DB4

23

DB3

24

DB2

25

DB1

26

DB0

27

PAEB

28

FLB

29

WCLKB

30

WENB

31

WXIB

32

VCC

33

PAFB

34

RXIB

35

FFB

36

WXOB/HFB

37

RXOB

38

102

LDA

101

OEA

100

RSA

99

VCC

98

GND

97

EFA

96

QA17

95

QA16

94

GND

93

QA15

92

VCC

91

QA14

90

QA13

89

GND

88

QA12

87

QA11

86

VCC

85

QA10

84

QA9

83

DB8

82

DB9

81

DB10

80

DB11

79

DB12

78

DB13

77

DB14

76

DB15

75

DB16

74

DB17

73

GND

72

RCLKB

71

RENB

70

LDB

69

OEB

68

RSB

67

VCC

66

GND

65

EFB

TQFP (PK128-1, ORDER CODE: PF)

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