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IDT723631

CMOS SyncFIFO 512 x 36, 1024 x 36, 2048 x 36

Integrated Device Technology 

IDT723631/723641/723651 CMOS SyncFIFO™

512 x 36, 1024 x 36, 2048 x 36

COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE

AND OPERATING FREE-AIR TEMPERATURE

Symbol

Parameter

IDT723631L15 IDT723631L20 IDT723631L30

IDT723641L15 IDT723641L20 IDT723641L30

IDT723651L15 IDT723651L20 IDT723651L30

Min. Max. Min. Max. Min. Max. Unit

fS

Clock Frequency, CLKA or CLKB

– 66.7 –

50

– 33.4 MHz

tCLK

Clock Cycle Time, CLKA or CLKB

15

–

20

–

30

–

ns

tCLKH Pulse Duration, CLKA or CLKB HIGH

6

–

8

–

12

–

ns

tCLKL Pulse Duration, CLKA or CLKB LOW

6

–

8

–

12

–

ns

tDS

Setup Time, A0-A35 before CLKA↑ and B0-B35 5

–

6

–

7

–

ns

before CLKB↑

tENS1 Setup Time, ENA to CLKA↑; ENB to CLKB↑

5

–

6

–

7

–

ns

tENS2 Setup Time, CSA, W/RA, and MBA to CLKA↑;

7

–

7.5

–

8

–

ns

CSB, W/RB, and MBB to CLKB↑

tRMS

tRSTS

tFSS

Setup Time, RTM and RFM to CLKB↑

Setup Time, RST LOW before CLKA↑

or CLKB↑(1)

Setup Time, FS0 and FS1 before RST HIGH

6

–

6.5

–

7

–

ns

5

–

6

–

7

–

ns

9

–

10

–

11

–

ns

tSDS(2) Setup Time, FS0/SD before CLKA↑

tSENS(2) Setup Time, FS1/SEN before CLKA↑

5

–

6

–

7

–

ns

5

–

6

–

7

–

ns

tDH

Hold Time, A0-A35 after CLKA↑ and B0-B35

0

–

0

–

0

–

ns

after CLKB↑

tENH1 Hold Time, ENA after CLKA↑; ENB after CLKB↑ 0

–

0

–

0

–

ns

tENH2 Hold Time, CSA, W/RA, and MBA after CLKA↑; 0

–

0

–

0

–

ns

CSB, W/RB, and MBB after CLKB↑

tRMH

Hold Time, RTM and RFM after CLKB↑

0

–

0

–

0

–

ns

tRSTH Hold Time, RST LOW after CLKA↑ or CLKB↑(1)

5

–

6

–

7

–

ns

tFSH

Hold Time, FS0 and FS1 after RST HIGH

0

–

0

–

0

–

ns

tSPH(2) Hold Time, FS1/SEN HIGH after RST HIGH

0

–

0

–

0

–

ns

tSDH(2) Hold Time, FS0/SD after CLKA↑

tSENH(2) Hold Time, FS1/SEN after CLKA↑

0

–

0

–

0

–

ns

0

–

0

–

0

–

ns

tSKEW1(3) Skew Time, between CLKA↑ and CLKB↑

for OR and IR

9

–

11

–

13

–

ns

tSKEW2(3) Skew Time, between CLKA↑ and CLKB↑

for AE and AF

12

–

16

–

20

–

ns

NOTES:

3023 tbl 06

1. Requirement to count the clock edge as one of at least four needed to reset a FIFO.

2. Only applies when serial load method is used to program flag offset registers.

3. Skew time is not a timimg constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB

cycle.

7

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