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IDT723631 Datasheet PDF : 23 Pages
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IDT723631/723641/723651 CMOS SyncFIFO™
512 x 36, 1024 x 36, 2048 x 36
COMMERCIAL TEMPERATURE RANGE
impedance control of the data outputs. If a port enable is LOW
during a clock cycle, the port chip select and write/read select
may change states during the setup- and hold time window of
the cycle.
When the output-ready (OR) flag is LOW, the next data
word is sent to the FIFO output register automatically by the
CLKB LOW-to-HIGH transition that sets the output-ready flag
HIGH. When OR is HIGH, an available data word is clocked
to the FIFO output register only when a FIFO read is selected
by the port-B chip select (CSB), write/read select (W/RB),
enable (ENB), and mailbox select (MBB).
SYNCHRONIZED FIFO FLAGS
Each IDT723631/723641/723651 FIFO flag is synchro-
nized to its port clock through at least two flip-flop stages. This
is done to improve the flags’ reliability by reducing the prob-
ability of metastable events on their outputs when CLKA and
CLKB operate asynchronously to one another. OR and AE are
synchronized to CLKB. IR and AF are synchronized to CLKA.
Table 4 shows the relationship of each flag to the number of
words stored in memory.
OUTPUT-READY FLAG (OR)
The output-ready flag of a FIFO is synchronized to the port
clock that reads data from its array (CLKB). When the output-
ready flag is HIGH, new data is present in the FIFO output
register. When the output-ready flag is LOW, the previous
data word is present in the FIFO output register and attempted
FIFO reads are ignored.
A FIFO read pointer is incremented each time a new word
is clocked to its output register. The state machine that
controls an output-ready flag monitors a write-pointer and
read-pointer comparator that indicates when the FIFO SRAM
status is empty, empty+1, or empty+2. From the time a word
is written to a FIFO, it can be shifted to the FIFO output register
in a minimum of three cycles of CLKB. Therefore, an output-
ready flag is LOW if a word in memory is the next data to be
sent to the FIFO output register and three CLKB cycles have
not elapsed since the time the word was written. The output-
ready flag of the FIFO remains LOW until the third LOW-to-
HIGH transition of CLKB occurs, simultaneously forcing the
output-ready flag HIGH and shifting the word to the FIFO
output register.
A LOW-to-HIGH transition on CLKB begins the first syn-
chronization cycle of a write if the clock transition occurs at
time tSKEW1 or greater after the write. Otherwise, the subse-
quent CLKB cycle may be the first synchronization cycle (see
Figure 6).
INPUT READY FLAG (IR)
The input ready flag of a FIFO is synchronized to the port
clock that writes data to its array (CLKA). When the input-
CSA
H
L
L
L
L
L
L
L
W/RA
X
H
H
H
L
L
L
L
ENA
X
L
H
H
L
H
L
H
MBA
X
X
L
H
L
L
H
H
CLKA
X
X
↑
↑
X
↑
X
↑
A0-A35 Outputs
In High-Impedance State
In High-Impedance State
In High-Impedance State
In High-Impedance State
Active, Mail2 Register
Active, Mail2 Register
Active, Mail2 Register
Active, Mail2 Register
Table 2. Port-A Enable Function Table
CSB
H
L
L
L
L
L
L
L
W/RB
X
L
L
L
H
H
H
H
ENB
X
L
H
H
L
H
L
H
MBB
X
X
L
H
L
L
H
H
CLKB
X
X
↑
↑
X
↑
X
↑
B0-A35 Outputs
In High-Impedance State
In High-Impedance State
In High-Impedance State
In High-Impedance State
Active, FIFO Output Register
Active, FIFO Output Register
Active, Mail1 Register
Active, Mail1 Register
Table 3. Port-B Enable Function Table
Port Functions
None
None
FIFO Write
Mail1 Write
None
None
None
Mail2 Read (Set MBF2 HIGH)
3023 tbl 09
Port Functions
None
None
None
Mail2 Write
None
FIFO read
None
Mail1 Read (Set MBF1 HIGH)
3023 tbl 10
10
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