IDT72205LB10JI8(2017) 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT72205LB10JI8
(Rev.:2017)

CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, and 4,096 x 18

Integrated Device Technology 

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFOTM

256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

PIN DESCRIPTION

Symbol

Name

I/O

Description

D0–D17 DataInputs

I Data inputs for a 18-bit bus.

RS

Reset

I When RS is set LOW, internal read and write pointers are set to the first location of the RAM array, FF and PAF

go HIGH, and PAE and EF go LOW. A reset is required before an initial WRITE after power-up.

WCLK WriteClock

I When WEN is LOW, data is written into the FIFO on a LOW-to-HIGH transition of WCLK, if the FIFO is not full.

WEN

Write Enable

I When WEN is LOW and LD is HIGH, data is written into the FIFO on every LOW-to-HIGH transition of

WCLK. When WEN is HIGH, the FIFO holds the previous data. Data will not be written into the FIFO if the FF

is LOW.

RCLK Read Clock

I When REN is LOW, data is read from the FIFO on a LOW-to-HIGH transition of RCLK, if the FIFO is not empty.

REN

Read Enable

I When REN is LOW, and LD is HIGH, data is read from the FIFO on every LOW-to-HIGH transition of RCLK.

When REN is HIGH, the output register holds the previous data. Data will not be read from the FIFO if the EF

is LOW.

OE

Output Enable

I When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a high-impedance

state.

LD

Load

I When LD is LOW, data on the inputs D0–D11 is written to the offset and depth registers on the LOW-to-HIGH

transition of the WCLK, when WEN is LOW. When LD is LOW, data on the outputs Q0–Q11 is read from the

offset and depth registers on the LOW-to-HIGH transition of the RCLK, when REN is LOW.

FL

First Load

I In the single deviceorwidthexpansionconfiguration, FL is grounded. In the depth expansion configuration, FL

is grounded on the first device (first load device) and set to HIGH for all other devices in the Daisy Chain.

WXI

Write Expansion

I In the single device or width expansion configuration, WXI is grounded. In the depth expansion configuration,

WXI is connected to WXO (Write Expansion Out) of the previous device.

RXI

Read Expansion I In the single device or width expansion configuration, RXI is grounded. In the depth expansion configuration,

RXI is connected to RXO (Read Expansion Out) of the previous device.

FF

Full Flag

O When FF is LOW, the FIFO is full and further data writes into the input are inhibited. When FF is HIGH, the FIFO

is not full. FF is synchronized to WCLK.

EF

Empty Flag

O When EF isLOW,theFIFOisemptyandfurtherdatareadsfromtheoutputareinhibited.When EF is HIGH, the

FIFO is not empty. EF is synchronized to RCLK.

PAE

Programmable

O When PAE is LOW, the FIFO is almost empty based on the offset programmed into the FIFO. The default

Almost-Empty Flag

offset at reset is 31 from empty for IDT72205LB, 63 from empty for IDT72215LB, and 127 from empty for

IDT72225LB/72235LB/72245LB.

PAF

Programmable

O When PAF is LOW, the FIFO is almost-full based on the offset programmed into the FIFO. The default offset at

Almost-Full Flag

reset is 31 from full for IDT72205, 63 from full for IDT72215LB, and 127 from full for IDT72225LB/72235LB/

72245LB.

WXO/HF WriteExpansion

Out/Half-Full Flag

O In the single device or width expansion configuration, the device is more than half full when HF is LOW. In the

depth expansion configuration, a pulse is sent from WXO to WXI of the next device when the last location in the

FIFO is written.

RXO

Read Expansion O In the depth expansion configuration, a pulse is sent from RXO to RXI of the next device when the last

Out

location in the FIFO is read.

Q0–Q17 DataOutputs

O Data outputs for an 18-bit bus.

VCC

Power

+5V power supply pins.

GND

Ground

Eight ground pins for the PLCC and seven gound pins for the TQFP/STQFP.

3

MARCH 2013

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