IDT7008L(2018) 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT7008L
(Rev.:2018)

HIGH-SPEED 64K x 8 DUAL-PORT STATIC RAM

Integrated Device Technology 

IDT7008S/L

High-Speed 64K x 8 Dual-Port Static RAM

AC Test Conditions

Input Pulse Levels

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

GND to 3.0V

5ns Max.

1.5V

1.5V

Figures 1 and 2

3198 tbl 11

Industrial and Commercial Temperature Ranges

5V

5V

DATAOUT

BUSY

INT

347Ω

893Ω

DATAOUT

30pF

347Ω

893Ω

5pF*

3198 drw 05

Figure 1. AC Output Test Load

3198 drw 06

Figure 2. Output Test Load

(for tLZ, tHZ, tWZ, tOW)

* Including scope and jig.

Waveform of Read Cycles(5)

tRC

ADDR

CE(6)

tAA(4)

(4)

tACE

tAOE (4)

OE

R/W

DATAOUT

BUSYOUT

tLZ (1)

VALID DATA(4)

tBDD (3,4)

tOH

tHZ (2)

3198 drw 07

Timing of Power-Up Power-Down

CE(6)

tPU

tPD

ICC

ISB

,

3198 drw 08

NOTES:

1. Timing depends on which signal is asserted last, OE or CE.

2. Timing depends on which signal is de-asserted first CE or OE.

3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY

has no relation to valid output data.

4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.

5. SEM = VIH.

6. Refer to Chip Enable Truth Table.

8

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